System and method for determining routes between circuit blocks

Details System and method for determining routes between circuit blocks System and method for determining routes between circuit blocks

1990-07-16

1994-05-03

Lee, Thomas C.

Boots, shoes, and leggings

364488, 364DIG2, 36491796, 395800, G06F 1560

Patent

active

053093720

ABSTRACT:
A system and method for automatically and optimally determining a route to be wired in a Programmable Logic Device (PLD) are disclosed in which a plurality of load pins to be wired with a source pin are selected sequentially according to a shortest length of distance from the source pin to the respective load pins, a plurality of switching stations present midway through each route of paths are selected on the basis of coordinates of a center of gravity derived from the coordinates of the unwired load pins and distances to the respective load pins to be wired sequentially, and, thus, a line network constituted by the routes of the first and second paths is formed. Furthermore, the route is corrected by searching out any of problematic switching stations through which the path cannot be formed from among the switching stations present along the route so as to bypass the problematic switching station. If this correction proves impossible, a second correction is sought by searching the problematic switching station itself so as to bypass a wired path present within the problematic switching station. If this correction also fails, a third mode of correction is implemented in which a switching station adjacent the problematic switching station is utilized.

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patent: 5113352 (1992-05-01), Finnerty
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"Designing With Logic Cell Arrays", Pardner Wynn, U.S. Conference Record, 13/4, Xilinx, Inc., pp. 1-9 and 13, 1987.
"Locusroute: A Parallel Global Router For Standard Cells", Jonathan Rose, Computer Systems Laboratory Paper 14.3, 25th ACM/IEEE Design Automation Conference, pp. 189-195, 1988.

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