System and method for determining acceptable logic cell location

Details System and method for determining acceptable logic cell location System and method for determining acceptable logic cell location

1996-03-06

1998-10-06

Voeltz, Emanuel Todd

Boots, shoes, and leggings

364490, 364491, G06F 1750

Patent

active

058187260

ABSTRACT:
A system and method for testing the placement of logic circuits on a regularly repeated array of integrated devices includes a base array memory, a basis memory, a floor plan memory, an array class memory, a logic cell index memory, a legal location index map memory, a legal location table memory and an engine. The system creates an array class for each type of device that is fabricated on the base array. The engine then tests each location of a basis of each array class for the legality of placing each logic cell of an associated group at that location. The engine then constructs a map of the array class, the legal location index map. Each entry on the map corresponds to a location in the array class, and each entry on the map contains a reference to a bit pattern. The engine also constructs a legal location table. The legal location table is a set of unique bit patterns that indicate the logic cells that may be placed at a location. The entries on the legal location index map reference bit patterns on the legal location table.

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