Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – Frequency of cyclic current or voltage
Reexamination Certificate
2001-06-28
2003-09-30
Nghiem, Michael (Department: 2863)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
Frequency of cyclic current or voltage
Reexamination Certificate
active
06628112
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to synchronous data detection, and more specifically, relates to a phase detection circuit that operates in multiple capacities of synchronous data detection.
BACKGROUND OF THE INVENTION
In systems for synchronous transmission of digital data, an information signal is sent from a transmitting unit to a receiving unit. This transmission may take place over serial or parallel data channels. In either case the data is sent in synchronism with a clock signal. In order to save bandwidth, the clock signal is normally not transmitted with the data. Hence, the receiving unit receives the signal at the same clock rate at which it is transmitted.
Two typical methods for transmitting digital data are baseband and carrier-based transmission. In baseband transmission, a signal is sent directly over a communications link. In carrier-based transmission, the signal is first modulated onto a carrier signal. The modulated carrier signal is then sent to the receiving unit. Common modulation techniques include amplitude modulation (AM), frequency modulation (FM) and phase modulation (PM). When a modulated signal reaches the receiving unit, it is demodulated from the carrier signal to its original form by demodulation circuitry.
The receiving unit then extracts the clock from the baseband or demodulated carrier-based signal in order to generate a reference by which the data can be interpreted. The method for extracting the clock depends on the type of data format used in the binary signal. Some examples of data formats are non-return to zero (NRZ), return to zero (RZ), biphase and delay-modulation.
Each format has associated advantages and disadvantages. The RZ format, for instance, contains a spectral line at the clock frequency, which makes clock recovery easy. The NRZ format, conversely, does not necessarily contain a spectral line at the clock frequency and requires additional circuitry for extraction. The NRZ format is advantageous in another way, however, in that it uses half the bandwidth as does the RZ format, which increases the amount of data that can be sent. Hence, data formats are chosen primarily by the needs and allowances of the particular application.
When using a format such as the NRZ format, the clock must be recovered from the signal. This operation is typically performed by a phase-locked loop (PLL). As depicted in
FIG. 1
, a PLL
100
typically comprises phase offset detection circuitry
102
, loop filter circuitry
104
and a voltage controlled oscillator (VCO). PLL
100
modulates VCO
106
until it is in phase with the incoming data. The signal generated by VCO
106
is then used as the reference clock to interpret the data signal.
In order to do this, phase detector circuit
102
detects the phase difference between the incoming data signal and the output of VCO
106
and generates phase detection signals
108
. Phase detection signals
108
have a difference in average value that corresponds to the difference in phase between the incoming data signal and the VCO
106
output. Loop filter
104
converts the difference in average value into an analog voltage signal and filters the signal to remove extraneous noise. An example analog voltage signal
200
is shown in FIG.
2
A. Signal
200
is fed to VCO
106
, which slows down or speeds up in response, bringing the output of VCO
106
into phase with the incoming data. Once aligned with the incoming data, the output of VCO
106
is used as the clock signal for interpreting incoming data
A conventional PLL circuit
300
containing a phase detector
330
is depicted in
FIG. 3. A
description and operating theory behind circuit
300
can be found in “A Self Correcting Clock Recovery Circuit,”
IEEE Journal of Lightwave Technology
, vol. LT-3, pp. 1312-1314, Dec. 1985. Circuit
300
provides a basic means for aligning data and clock phase and comprises phase detector
330
, loop filter
328
and VCO
314
.
Phase detector
330
comprises two D flip flops
302
and
304
connected in series, and two XOR gates
306
and
308
tied to the input and output of, respectively, flip-flops
302
and
304
. Incoming data is supplied to input node
310
of flip-flop
302
and the input of XOR gate
306
. VCO
314
provides a clock signal to flip-flop
302
at its clock input node
316
. D flip-flop
302
enables its output
312
on every rising edge of this clock signal. Output
312
is connected directly to the input of XOR gates
306
and
308
, as well as to the input to D flip-flop
304
. D flip-flop
304
enables its output
318
on the rising edge of the inverted clock signal provided by VCO
314
. Hence, flip-flops
302
and
304
operate one-half clock cycle apart. The output
318
of D flip-flop
304
is connected to the second input of XOR gate
308
.
Phase detector
330
produces two phase detection signals by which the phase offset is measured. The phase detection signals, commonly referred to as reference signals, are square pulse signals generated for each transition of the incoming data and having a fixed width equal to half the clock period. The first phase detection signal is output
324
of XOR gate
308
. It is a square pulse signal commonly referred to as a reference signal that is generated for every transition of the incoming data and has a fixed width equal to half the clock period.
The second phase detection signal is provided by the output
322
of XOR gate
306
. The second phase detection signal is a variable width, square pulse signal with a pulse generated for every transition of the incoming data. The width of this square pulse is dependent upon the position of the rising clock edge in relation to each incoming data transition. This signal is commonly referred to as an error signal. When the rising edge of the clock is in phase with the incoming data, the width of the data pulses produced in the error and reference signals are the same. There is no difference in average value between the signals and correspondingly, the frequency of VCO
314
is not modulated.
When the rising edge of the clock lags behind the incoming data transition, the data pulse in the error signal decreases in width and has an average value less than the fixed width pulse of the reference signal. As a result, a negative error voltage is produced by loop filter
328
and fed to VCO
314
. When the rising edge of the clock arrives before the incoming data transition, the data pulse in the error signal increases in width and has an average value more than the fixed width pulse of the reference signal. As a result, a positive error voltage is produced by loop filter
328
and fed to VCO
314
.
As data frequencies rise, the delay, hold and setup times associated with circuit
300
become smaller in order to accommodate shorter data pulse widths and to guard against timing violations. However, phase detector
300
will begin to experience difficulty at these higher frequencies. Properly balancing propagation delays and drive strengths of the D flip-flops
302
and
304
becomes very difficult. In order for the flip-flops to be powerful enough to drive their outputs to satisfy shorter hold and setup times, they must be larger in terms of circuit geometry. But as their size increases, the distance the distance that data signal
310
must travel also increases and creates longer propagation delays. The propagation delays will begin to violate the hold and setup times of the various logic gates and the circuit will fail to recognize data pulses. These pulses are generally referred to as “missed pulses.” Missed pulses can translate into a “dead zone” in the analog voltage signal at the phase detector output, resulting in phase jitter. An analog voltage signal
202
with a dead zone
204
is demonstrated in FIG.
2
B.
Phase jitter is a time variation in the clock edge produced by VCO
106
, in which the edge moves back and forth instantaneously and oscillates around the targeted position. This is undesirable because it results in a dynamically varying amount of time available for logic computations. P
Conexant Systems Inc.
Nghiem Michael
SEED IP Law Group PLLC
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