System and method for detecting NOR gates and NAND gates

Details System and method for detecting NOR gates and NAND gates System and method for detecting NOR gates and NAND gates

1999-01-26

2000-06-20

Bowers, Charles

Semiconductor device manufacturing: process

Including control responsive to sensed condition

Electrical characteristic sensed

H01L 2100

Patent

active

060777176

ABSTRACT:
A method is provided for identifying a NOR gate from a netlist. The method operates by first identifying at least one static gate output node, and then, for that at least one static gate output node, evaluating all channel-connected field effect transistors (FETs) that are electrically connected to the at least one static gate output node to ensure that: (i) no PFET (p-channel FET) that is channel connected to the at least one static gate output node is directly connected to VDD, (ii) all NFETs (n-channel FETs) that are channel connected to drive the at least one static gate output node are directly connected to ground, and (iii) at least one PFET and at least one NFET are channel connected to the at least one output node. A method is also provided for identifying a NAND gate from a netlist by identifying at least one static gate output node, then, for the at least one static gate output node, evaluating all channel-connected field effect transistors (FETs) that are electrically connected to the at least one static gate output node to ensure that: (i) all PFETs (p-channel FET) that are channel connected to drive the at least one static gate output node are directly connected to VDD, (ii) no NFETs (n-channel FETs) that are channel connected to the at least one static gate output node are directly connected to ground, and (iii) at least one PFET and at least one NFET are channel connected to the at least one output node.

REFERENCES:
patent: 5210699 (1993-05-01), Harrington
patent: 5696771 (1996-05-01), Beausang et al.
patent: 5889685 (1999-03-01), Ramachandran

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