Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2000-03-31
2001-09-04
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S020000, C714S025000, C326S083000
Reexamination Certificate
active
06285975
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the simulation of an integrated circuit's operation prior to the manufacture of the circuit and, more particularly, to detecting floating nodes (or transistor gates) within a netlist of nodes representing the circuit.
2. Description of the Related Art
Integrated circuits are highly complex and must be tested during production to ensure high quality and reliability. One of many tests which may be performed is a test of the current drawn by the circuit while in a static mode. This test may be referred to as a static current test or IDDQ test. The IDDQ test entails applying a power supply to the circuit and putting the circuit into an IDDQ test mode state (e.g., by clocking selected inputs for a predetermined time period and then waiting for the circuit to settle into the desired state). Once the circuit is in the IDDQ test mode state, current readings are taken between the power supply and ground.
When integrated circuits are production tested, large IDDQ values are often indicative of process failures. This is particularly true for CMOS circuits which typically have very small IDDQ values. Thus IDDQ values are often used for quality screening to eliminate potentially unreliable parts before they are sold. However, the usefulness of IDDQ values for quality screening may be undermined when an integrated circuit has a large IDDQ value due to floating transistor gates that are part of the design, i.e., not due to a process failure. For this reason, it is advantageous to design an IDDQ test mode into the integrated circuit that properly disables all analog circuitry, dynamic logic, and other circuitry that might cause current to flow, e.g., transistors whose control terminals (or “gates”) are not tied to a power supply or ground (i.e., “floating”). Note that control terminals holding a decayed capacitive charge and not coupled to any power supplies or ground are considered to be floating transistor gates.
However, when designing an IDDQ test mode it is no simple task to eliminate all floating transistor gates or guarantee that all such transistors will not provide a current path from VCC to ground (or VSS). This is in part due to the large number of transistors involved in modern integrated circuits and the independent or block-oriented nature of the design process. For these reasons, a method for easily detecting floating transistor gates at the design stage is needed.
One possible solution is software modeling. Most integrated circuits can be modeled in software. Various software languages and circuit simulation applications (e.g., SPICE and Star-SIM™) currently exists for that purpose. Using these languages and applications, a list of nodes and components between nodes can be fashioned. These lists are often referred to as “netlists.” Using a netlist, circuit simulation applications can be used to determine if the integrated circuit being designed will function according to specifications. If a failure is detected, the circuit design can be modified prior to embodying the circuit upon silicon. Modeling and simulating an integrated circuit in software advantageously minimizes the time and cost associated with producing a viable integrated circuit.
However, using software to identify with certainty which transistor gates or nodes, if any, are floating is difficult because of inherent limitations within the simulation software. For these reasons, a method for easily detecting floating nodes in a netlist is desired. Furthermore, it would also be desirable for the method to work regardless of whether the netlist represents an analog, digital, or mixed-signal integrated circuit.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a method for detecting floating transistor gates within a netlist in accordance with the present invention. In one embodiment, the method comprises identifying each unique input node within the netlist that is coupled to a transistor gate. These input nodes are then used to generate a resistor netlist or “card.” The resistor card is used in conjunction with the original netlist during circuit simulation to couple two resistors to each unique input node. The first resistor is coupled between the input node and a high potential, e.g., the positive terminal of a power supply. The second resistor is coupled between the input node and a lower potential, e.g., the negative terminal of a power supply or ground. The resistors may be configured to have equal resistance values. The resistance values may also be large enough to ensure that the current conducted through the resistors will be minimal in relation to the current drawn through a transistor when the gate's input node is floating. The two resistors operate in combination to pull the input node to a voltage level near the midpoint between the high and low potentials (e.g., between power supply and ground voltage levels) when the input node is floating (i.e., not driven to a high or low potential). The resistance values may be low enough to ensure that the midpoint voltage is reached, regardless of any leakage currents in the circuit. This midpoint voltage level turns on both transistors in the gate and consequently produces a relatively large current between the power supply and ground. Advantageously, this large current is easily detectable from the simulation output and may be used to locate which, if any, transistor gates are floating.
In an alternative embodiment, the resistors connected to the identified nodes (and the power supply and ground which feed those resistors) may be separated into a second database. As a result, currents detected through the source-drain path of the transistors may be easily distinguished from currents read through the resistors. Advantageously, this embodiment allows circuits with an extremely large number of gates to be simulated without losing the ability to easily discern which currents are attributable to floating transistor gates and which currents are attributable to the added resistors.
Also contemplated is a method of modeling floating transistor gates within an integrated circuit simulation application. In one embodiment the method comprises receiving a netlist circuit model of an integrated circuit as input. The netlist may comprise a plurality of nodes, some of which may be connected to transistor gates. The netlist is searched to identify any unique input nodes. Unique input nodes are single instances of nodes that are connected to one or more transistor gates. Finally, two resistors are connected to each identified unique input node. The first resistor is coupled between the input node and a low potential. The second resistor is coupled between the input node and a high potential. Advantageously, floating transistor gates may be easily detected during circuit simulation by the large currents they will conduct.
An apparatus for determining static current failures within an integrated circuit modeled as a netlist is also contemplated. In one embodiment the apparatus comprises a plurality of transistors and nodes contained within a netlist, a power supply and ground, a plurality of resistors, and a current meter. The power supply and ground are coupled to the plurality of transistors according to the netlist. The resistors are divided into two groups, i.e., pull-up resistors and pull-down resistors. Pull-up resistors are coupled between the power supply and a number of selected nodes, while pull-down resistors are coupled between ground and the selected nodes, wherein the selected nodes are unique nodes coupled to the control terminals (i.e., gates) of one or more transistors. The current meter is coupled between the power supply and ground and is used to determine if current flowing between the power supply and ground is greater than a pre-defined limit indicative of static current failure.
Another method contemplated comprises scanning a netlist to detect unique input nodes that are coupled to control terminals of transistors, wherein the netlist ma
Holifield Ronald D.
Nair Vijayakumaran V.
Conley & Rose & Tayon P.C.
Legarity, Inc.
Phan Thai
Teska Kevin J.
LandOfFree
System and method for detecting floating nodes within a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for detecting floating nodes within a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for detecting floating nodes within a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2530173