Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-08-10
2001-01-23
Brown, Glenn W. (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S501000, C324S750010, C324S765010, C324S602000, C324S603000, C324S719000
Reexamination Certificate
active
06177802
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to a system and method for detecting defects in an interlayer dielectric interposed between conductive lines of a semiconductor device, and more particularly relates to enhancing carriers in the dielectric and deflecting the carriers toward the dielectric surface via the Hall-effect.
BACKGROUND OF THE INVENTION
There is an increasing demand for miniaturization in the integrated circuits industry. This demand has led to an ever constant reduction in separation between conductive lines (e.g., metal lines) in order to reduce integrated circuit size and/or increase density. The reduced spacing between the conductive lines has the undesirable effect of increasing the capacitance of whatever material lies between the conductive lines. This phenomenon is known as capacitive crosstalk.
In the past, overall integrated circuit (IC) performance depended primarily on device properties; however, this is no longer the case. Parasitic resistance, capacitance and inductance associated with interconnections and contacts of an IC are beginning to become increasingly significant factors in IC performance. In current IC technology, the speed limiting factor is no longer device delay, but the resistive-capacitive (RC) delays associated with the conductive interconnections (e.g., metal lines) of the IC.
Conventional ICs typically employ an interconnect structure wherein a first conductive line is adjacent a second conductive line. If the crosstalk or capacitance between the first conductive line and the second conductive line is high, then the voltage on the first conductive line alters or affects the voltage on the second conductive line. This alteration in voltage may result in the IC being inoperable as a result of misinterpreting logic zeros, logic ones and voltage levels, and consequently incorrectly processing binary and/or analog information.
In order to reduce capacitive coupling and therefore reduce capacitive crosstalk, low dielectric constant (low-K) materials have been developed to lie between conductive lines in order to insulate one conductive line from the other.
FIG. 1
illustrates a portion of a typical integrated circuit. An insulating layer is formed on a semiconductor substrate, both the insulating layer and substrate are generally indicated at
20
. A conductive pattern
22
including conductive lines
24
is formed over the insulating/substrate layer
20
. The conductive lines
24
are separated by interwiring spaces
26
formed on the insulating/substrate layer
20
. A dielectric material
30
(e.g., silicon dioxide, spin on glass) is shown deposited over the conductive lines
24
and the interwiring spaces
26
so as to form an insulative barrier
32
(interlayer dielectric) between the conductive lines
24
.
Dielectric materials such as silicon dioxide are susceptible to ion contamination and moisture penetration. Furthermore, current deposition and polishing techniques have not reached a level where contamination of the interlayer dielectric (ILD) is eliminated. Additionally, voids within the ILD may result due to an imperfect fabrication process. Contaminants are undesirable in the ILD because the contaminants may degrade the performance of the ILD and facilitate unwanted capacitive crosstalk (e.g., leakage) between adjacent metal lines. Voids are not desired because the voids weaken the ILD and may lead to the formation of cracks within the ILD which may also give rise to leakage of current between adjacent conductive lines.
Detection of such defects (e.g., lattice defects, dislocations, impurities, contaminants and voids) is typically performed at the end of the process line after the IC is substantially complete. However, the in-line fabrication of the IC represents up to 95% of the cost of the ultimate integrated circuit. Thus, it would be desirable to test the IC during fabrication in order to detect defects in the IC early on before additional monies and man hours are spent down the line for later fabrication steps.
In view of the above, it would be desirable to have a system and method for in-line detection of defects in the interlayer dielectric of an integrated circuit.
SUMMARY OF THE INVENTION
The present invention provides for a system and method for in-line detection of defects (e.g., lattice defects, dislocations, impurities, contaminants and voids) in an interlayer dielectric between adjacent conductive lines of an integrated circuit. More particularly, the present invention applies a bias voltage between a first set of conductive lines of an IC lying adjacent each other along a first plane so as to induce a leakage current to flow between the first set of conductive lines across the ILD separating the first set of conductive lines. The applied voltage is preferably applied at a level coincident with the operating voltage of the IC so as to avoid breakdown of any components of the IC. A radiation source or light source (e.g., ultraviolet (UV) laser) is applied at the portion of the ILD where leakage current flow is being induced. The light source provides for enhancing the flow of leakage current at the ILD portion being tested for defects. More particularly, by applying a light source (preferably UV) with an energy level greater than the energy barrier between the metal of the conductive lines and the dielectric (≈3.2eV in the case of SiO
2
) carriers are injected into the dielectric from the metal. This results in the leakage current flow being enhanced.
The biased ILD material is subjected to a magnetic field which is oriented in a direction orthogonal to the current path. The magnetic field deflects carriers associated with both the defects and light source toward a surface of the ILD in accordance with the Hall-effect. The deflected carriers, after reaching the ILD, form an accumulated charge profile in the vicinity of the ILD surface. The charge profile is manifested as a Hall voltage across a second set of conductive lines lying adjacent each other along a second plane perpendicular to the first plane. The ILD material being tested also being interposed between the second set of conductive lines.
The Hall voltage is measured using a Hall-voltage monitor operatively coupled to the second set of conductive lines. If defects (e.g., lattice defects, dislocations, impurities, contaminants and voids) are present within the portion being tested, the amount of leakage current flow will differ from an expected value if the defects were not present. This is because some types of defects may result in the presence of trapping sites within the ILD. As a result of the trapping sites less energy may be required to excite electrons across the band-gap than if the dielectric was free of trapping sites. The light source not being sufficient to excite carriers across the band-gap of the dielectric will generate carriers substantially only at the trapping sites. Accordingly, the presence of such type of defect in the ILD may increase the amount of current flowing across the dielectric as compared to if the defect were not present. Additionally, the defect site may create an energy barrier between the metal and dielectric which is less than 3.2 eV. In such a case, more carriers may be injected at the defect site. By selectively choosing the light energy to be less than 3.2 eV or close to 3.2 eV the impact on leakage current associated with a defective site as compared to a normal site is enhanced. With respect to voids, the amount of current flow detected will be less than if the voids were not present. Accordingly, the amount of leakage current is directly related to the amount of carriers activated or excited which in turn corresponds to the Hall voltage measured along the second set of conductive lines. By monitoring for a decrease in Hall voltage below an expected level the presence of voids may be determined. Thus, by monitoring for a change in Hall voltage above and/or below an expected level the presence of defects in the ILD may be detected. By selectively scanning the light source across a predefined ma
Liu Yowjuang William
Shabde Sunil N.
Tsui Ting Yiu
Advanced Micro Devices , Inc.
Amin, Eschweiler & Turocy, LLP
Brown Glenn W.
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