Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
2000-02-03
2001-11-27
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S158000, C327S293000, C327S149000
Reexamination Certificate
active
06323714
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to synchronous clock distribution in a very large scale integrated (VLSI) circuit, and more particularly, to a system and method for actively controlling synchronous clock skewing in a clock signal distribution network across an entire VLSI circuit.
BACKGROUND OF THE INVENTION
VLSI circuit chips require a clocking scheme in order to execute instructions and transfer data across the many individual smaller circuit components. Ideally, clock signals would arrive at every circuit element within a VLSI circuit simultaneously. As a result, clock distribution networks in VLSI circuits have typically been designed such that the reference clock signal is distributed in a symmetric manner across the circuit from a centrally located clock reference. A balanced “H,” a grid, a spine, and a tree are some examples of the physical layout of clock distribution networks across a VLSI chip.
Despite the symmetry associated with prior art clock distribution networks, imperfections in circuit conductors and clock signal repeaters, lead to random variations across the clock distribution network on a VLSI chip. These random variations introduced by flaws in manufacturing processes introduce clock skew. Clock skew is further affected by the different logic blocks implemented on a VLSI circuit. Since logic blocks perform different functions, it follows that each logic block is implemented with a different circuit stricture. Thus, during operation, the path taken in any given logic block varies from block to block. Different capacitive and resistive loads caused by the various logic elements also affect clock skew. In other words, different logic circuits and variations within the elements from logic block to logic block make it nearly impossible to match the rising and falling edges of different clocks across each individual logic block on a VLSI circuit.
Early generations of VLSI circuits used a single clock with a 50% duty cycle. Only a single operation could be performed during each individual clock cycle. As higher clock frequencies became not only desirable, but required, various schemes were employed to increase the allowable frequency of the clock cycle, for example, altering the duty cycle to increase the enable phase and to decrease the disable phase while maintaining the smallest possible clock period. A clear problem with this method was that the maximum allowable clock frequency was limited to the setup and hold time requirements of the individual physical components on the VLSI circuit. Other methods were needed to increase clock frequency.
One method for permitting greater clock frequency is known as “pipelining.” In this method, a dual phase clock scheme is used by generating a differential pair of symmetric clocks in a centralized region of the VLSI circuit. In a simple “pipeline” configuration, logic for implementing operations is divided into specific “pipeline” stages, whereby each stage represents one clock cycle. Alternating stages receive the differential clock signals. Thus, while a given pipeline stage performs an operation during an enable phase, the subsequent pipeline stage, which depends on the output from the previous stage, waits during its disable cycle. As one of the differential clocks enters the disable cycle, the other differential clock enters the enable cycle, and the subsequent pipeline stage performs its designated operation.
Since typical pipelined clocking schemes generally use global clocks and a clock distribution network to apply the global clock to localized circuit blocks across the VLSI circuit, clock skew and the rise and fall times of the clocking signals received by each individual circuit blocks on a VLSI circuit are critical to circuit performance.
Clock skew reduces circuit performance by introducing race conditions and hold time problems. Race conditions occur when a first latch designed to maintain a data signal at a particular level for sampling by a circuit in a second clock zone on the VLSI circuit transitions prior to the sampling event. Race conditions introduce data transfer errors when the receiving circuit applies incorrect data. In a related manner, clock skew introduces hold time problems as clock signal delays at a data sending circuit reduce the time available for a data signal to reach a receiving circuit in a second clock zone. As a result of clock skew, the VLSI circuit can not be run as fast as intended. Clock skew is a function of load, clock network distribution across the dice and device mismatch, as well as, temperature and voltage gradients across the VLSI circuit.
Thus, a need exists in the industry to control clock skew between logic blocks across a VLSI circuit.
SUMMARY OF THE INVENTION
It is thus an object of the present invention to actively control clocks across the different individual circuits on a VLSI circuit chip by eliminating clock skew.
These and other objectives are accomplished by the system and method of the present invention. Each local circuit within a VLSI circuit is provided with a local clock via a clock distribution network. A local clock buffer strengthens and further distributes a clock signal within its local circuit. The present invention provides a system and method for actively deskewing synchronous clocks in a VLSI circuit by introducing a controllable delay unit at each local clock buffer.
Briefly described, in architecture, the system can be added to any of a number of various clock distribution networks on a VLSI circuit through the introduction of controllable clock zone buffers and phase comparators. By actively adjusting each localized delay unit in response to measured clock phase differences from adjacent circuit zones, clock skew problems can be minimized across clock zones on a VLSI circuit.
The present invention can also be viewed as providing a method for actively controlling clock skew across the individual logic blocks of a VLSI circuit chip. In this regard, the method can be broadly summarized by the following steps. First, providing a synchronous clock to each of a plurality of clock zones. Second, introducing a controllable delay element within the local clock buffer in each of the plurality of clock zones. Third, comparing the phase of two or more zone clock signals from adjacent zones to create a control signal. Fourth, using the control signal to adjust the delay element in a particular clock zone in response to the phase comparison result. Last, repeating the steps of comparing clock signals and adjusting clock buffer delays during each clock cycle across the VLSI circuit.
In a preferred embodiment, the steps of comparing and adjusting clock delays are referenced from a centrally located reference clock so that the reference clock is distributed across each of the clock zones in a “tree” topology. In this embodiment, the first level phase comparisons resemble branches with the centrally located clock reference representing the trunk. As the process steps of comparing and adjusting progress, each phase comparison of local adjacent clocks branches further from the trunk of the tree. In the “tree” topology, each clock zone signal is compared with at least one clock signal from an adjacent clock that is more proximate to a centrally located reference clock.
In another preferred embodiment, the step of comparing the phase of clock signals is performed across a number of adjacently located clock zones with each individual clock zone adjusted in response to comparisons with clock signals from two or more adjacent clock zones. This “regional” or “hierarchical” approach to clock zone delay adjustment has the property that each particular clock zone not only has a direct impact on the delay adjustment for adjacent clock zones, but the adjacent clock zones, also impact the ultimate delay correction for each of their adjacent clock zones as well.
In a configuration well known in the prior art, a clock signal from one of the clock zones furthest removed from the centrally located reference clock (both embodiments) is used as a
Berta Eugene Z
Blair Gerard M
Naffziger Samuel D
Wells James Steven
Cunningham Terry D.
Hewlett--Packard Company
Tra Quan
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