System and method for design verification

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C703S015000, C703S016000, C703S017000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C714S739000, C714S741000, C714S742000

Reexamination Certificate

active

09962827

ABSTRACT:
An extractor extracts descriptions unexecuted in the logic simulation according to code coverage information for the circuit description. An examiner examines whether or not there is a possibility of executing the extracted unexecuted descriptions. A prohibited-input-checker generator generates a test pattern. The test pattern is to execute descriptions including unexecuted descriptions that there is a possibility of executing and excluding unexecuted descriptions that there is no possibility of executing as determined by the examiner. The prohibited-input-checker generator also generates a prohibited-input checker to check whether or not an input pattern of a logic simulation to be carried out is equal to an input pattern of the test pattern to execute the unexecuted description if the test bench is regarded as a prohibited input under a specification at a logic simulation using the test pattern to execute the unexecuted description.

REFERENCES:
patent: 5604895 (1997-02-01), Raimi
patent: 5841674 (1998-11-01), Johannsen
patent: 6132109 (2000-10-01), Gregory et al.
patent: 6487704 (2002-11-01), McNamara et al.
patent: 6523151 (2003-02-01), Hekmatpour
patent: 6530054 (2003-03-01), Hollander
patent: 6775810 (2004-08-01), Chang et al.
patent: 6816825 (2004-11-01), Ashar et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

System and method for design verification does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for design verification, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for design verification will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3895668

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.