Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle
Reexamination Certificate
2010-05-18
2011-11-22
Levin, Naum (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
C430S005000
Reexamination Certificate
active
08065636
ABSTRACT:
A system and a method for creating a focus-exposure model of a lithography process are disclosed. The system and the method utilize calibration data along multiple dimensions of parameter variations, in particular within an exposure-defocus process window space. The system and the method provide a unified set of model parameter values that result in better accuracy and robustness of simulations at nominal process conditions, as well as the ability to predict lithographic performance at any point continuously throughout a complete process window area without a need for recalibration at different settings. With a smaller number of measurements required than the prior-art multiple-model calibration, the focus-exposure model provides more predictive and more robust model parameter values that can be used at any location in the process window.
REFERENCES:
patent: 5558963 (1996-09-01), Tsudaka et al.
patent: 5723235 (1998-03-01), Tsudaka et al.
patent: 6749972 (2004-06-01), Yu
patent: 6828542 (2004-12-01), Ye et al.
patent: 6884984 (2005-04-01), Ye et al.
patent: 6913861 (2005-07-01), Shishido et al.
patent: 6954911 (2005-10-01), Pierrat
patent: 7003758 (2006-02-01), Ye et al.
patent: 7049589 (2006-05-01), Yamaguchi et al.
patent: 7224437 (2007-05-01), Percin et al.
patent: 7336341 (2008-02-01), Mimotogi et al.
patent: 7352453 (2008-04-01), Mieher et al.
patent: 7444615 (2008-10-01), Percin et al.
patent: 7470492 (2008-12-01), Bigwood et al.
patent: 7473495 (2009-01-01), Tanaka et al.
patent: 7488933 (2009-02-01), Ye et al.
patent: 7588868 (2009-09-01), Zach et al.
patent: 7791732 (2010-09-01), Den Boef et al.
patent: 2004/0156030 (2004-08-01), Hansen
patent: 2004/0190008 (2004-09-01), Mieher et al.
patent: 2004/0195507 (2004-10-01), Yamaguchi et al.
patent: 2005/0166174 (2005-07-01), Ye et al.
patent: 2006/0206851 (2006-09-01), Van Wingerden et al.
patent: 2006/0273266 (2006-12-01), Preil et al.
patent: 07-175204 (1995-07-01), None
patent: 2000-232057 (2000-08-01), None
patent: 2003-164797 (2003-06-01), None
patent: 2003-243291 (2003-08-01), None
patent: 2005-217378 (2005-08-01), None
patent: 2006-512758 (2006-04-01), None
patent: 2009-105430 (2009-05-01), None
Japanese Office Action mailed Feb. 16, 2011 in corresponding Japanese Patent Application No. 2008-526083.
Y Cao et al. “Optimized Hardware and Software for Fast, Full Chip Simulation” Proc. SPIE vol. 5754, pp. 407-414, (2005).
B.J. Lin “The Exposure-Defocus Forest” Jpn. J. Appl. Phys. vol. 33, pp. 6756-6764 (1994).
A. Borjon et al. “High Accuracy 65nm OPC Verification: Full Process Window Model vs. Critical Failure ORC” Proc. SPIE vol. 5754, pp. 1190-1201 (2005).
B. Tollkuhn et al. “Do We Need Complex Resist Models for Predictive Simulation of Lithographic Process Performance?” Proc. SPIE vol. 5376, pp. 983-994 (2004).
Cao Yu
Chen Luoqi
Liu Hua-Yu
Ye Jun
ASML Netherlands B.V.
Levin Naum
Pillsbury Winthrop Shaw & Pittman LLP
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