System and method for correcting an inaccurate clock

Data processing: measuring – calibrating – or testing – Calibration or correction system – Timing

Reexamination Certificate

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C702S085000

Reexamination Certificate

active

11066375

ABSTRACT:
System and method for correcting an inaccurate clock with the use of an accurate reference clock. A preferred embodiment comprises repeatedly counting clock cycles in a clock signal generated by the inaccurate clock for a specified period of time, after the completion of each specified period of time, computing a delta value based on the clock cycle counts of the clock signal of the inaccurate clock, accumulating a delta sum value, and computing a clock adjustment value for the inaccurate clock based upon the delta sum value. The reference clock is used to mark the end of each specified period of time.

REFERENCES:
patent: 5915108 (1999-06-01), Frey et al.
patent: 6121816 (2000-09-01), Tonks et al.
Hamoui, A.A., et al., “Delta-Sigma Modulator Topologies for High-Speed High-resolution A/D converters,” 2002, pp. I-356-I-359, IEEE.
Papamichalis, P.E., et al., “Delta Coding of LPC Parameters,” 1983, ICASSP 83, pp. 85-88, IEEE, Boston.
Zierhofer, C.M., “Numerical Adaptive Delta Modulation—A technique for Digital Signal Representation in ASIC Applications,” 1991, pp. 331-334, IEEE.

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