Data processing: software development – installation – and managem – Software program development tool – Testing or debugging
Reexamination Certificate
2007-11-20
2007-11-20
Thomson, William (Department: 2194)
Data processing: software development, installation, and managem
Software program development tool
Testing or debugging
C717S132000, C717S156000, C716S030000
Reexamination Certificate
active
10285399
ABSTRACT:
An embodiment of the invention includes a method of forming a control-dataflow graph that includes separating a control flow graph into two or more basic blocks, and converting said two or more basic blocks into code blocks, where the code blocks are formed into the control-dataflow graph. Another embodiment of the invention includes a method of forming a control-dataflow graph that includes separating a control flow graph into two or more basic blocks, forming a lode node in at least one of said basic blocks, forming a store node in at least one of said code blocks, inserting a delay node in at least one of said code blocks, segregating external hardware logic modules from said control flow graph, and converting said two or more basic blocks into code blocks, wherein the code blocks are formed into the control-dataflow graph.
REFERENCES:
patent: 5230057 (1993-07-01), Shido et al.
patent: 5303377 (1994-04-01), Gupta et al.
patent: 5570040 (1996-10-01), Lytle et al.
patent: 5737766 (1998-04-01), Tan
patent: 5831864 (1998-11-01), Raghunathan et al.
patent: 5870588 (1999-02-01), Rompaey et al.
patent: 5892962 (1999-04-01), Cloutier
patent: 5903771 (1999-05-01), Sgro et al.
patent: 5978588 (1999-11-01), Wallace
patent: 6023755 (2000-02-01), Casselman
patent: 6052773 (2000-04-01), DeHon et al.
patent: 6076152 (2000-06-01), Huppenthal et al.
patent: 6192439 (2001-02-01), Grunewald et al.
patent: 6202204 (2001-03-01), Wu et al.
patent: 6226776 (2001-05-01), Panchul et al.
patent: 6401187 (2002-06-01), Motokawa et al.
patent: 6745384 (2004-06-01), Biggerstaff
patent: 6762764 (2004-07-01), Hiwada et al.
patent: 2002/0056078 (2002-05-01), Inagaki et al.
patent: 2002/0095666 (2002-07-01), Tabata et al.
patent: 2002/0095667 (2002-07-01), Archambault
patent: 2003/0066061 (2003-04-01), Wu et al.
patent: 2003/0101419 (2003-05-01), Yamashita et al.
patent: 2003/0137518 (2003-07-01), Hiwada et al.
patent: 2003/0140337 (2003-07-01), Aubury
patent: 2004/0003220 (2004-01-01), May et al.
Kramer, R.; Gupta, R.; Soff, M.; “The Combining DAG: A Technique for Parallel Data Flow Analysis”; IEEE Transactions on Parallel and Distributed Systems; vol. 5, Issue 8, pp. 805-813, Aug. 1994.
Agarwal, A., et al., “The Raw Compiler Project”, pp. 1-12, http://cag-www.lcs.mit.edu/raw, Proceedings of the Second SUIF Compiler Workshop, Aug. 21-23, 1997.
Albaharna, Osama, et al., “On the viability of FPGA-based integrated coprocessors”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 206-215.
Amerson, Rick, et al., “Teramac—Configurable Custom Computing”, © 1995 IEEE, Publ. No. 0-8186-7086-X/95, pp. 32-38.
Barthel, Dominique Aug. 25-26, 1997, “PVP a Parallel Video coProcessor”, Hot Chips IX, pp. 203-210.
Bertin, Patrice, et al., “Programmable active memories: a performance assessment”, © 1993 Massachusetts Institute of Technology, pp. 88-102.
Bittner, Ray, et al., “Computing kernels implemented with a wormhole RTR CCM”, © 1997 IEEE, Publ. No. 0-8186-8159-4/97, pp. 98-105.
Buell, D., et al. “Splash 2: FPGAs in a Custom Computing Machine—Chapter 1—Custom Computing Machines: An Introduction”, pp. 1-11, http://www.computer.org/espress/catalog/bp07413/spls-ch1.html (originally believed published in J. of Supercomputing, vol. IX, 1995, pp. 219-230.
Casselman, Steven, “Virtual Computing and The Virtual Computer”, © 1993 IEEE, Publ. No. 0-8186-3890-7/93, pp. 43-48.
Chan, Pak, et al., “Architectural tradeoffs in field-programmable-device-based computing systems”, © 1993 IEEE, Publ. No. 0-8186-3890-7/93, pp. 152-161.
Clark, David, et al., “Supporting FPGA microprocessors through retargetable software tools,”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 195-103.
Cuccaro, Steven, et al., “The CM-2X: a hybrid CM-2/Xilink prototype”, © 1993 IEEE, Publ. No. 0-8186-3890-7/93, pp. 121-130.
Culbertson, W. Bruce, et al., “Exploring architectures for volume visualization on the Teramac custom computer”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 80-88.
Culbertson, W. Bruce, et al., “Defect tolerance on the Teramac custom computer”, © 1997 IEEE, Publ. No. 0-8186-8159-4/97, pp. 116-123.
Dehon, Andre, “DPGA-Coupled microprocessors: commodity IC for the early 21stcentury”, © 1994 IEEE, Publ. No. 0-8186-5490-2/94, pp. 31-39.
Dehon, A., et al., “MATRIX A Reconfigurable Computing Device with Configurable Instruction Distribution”, Hot Chips IX, Aug. 25-26, 1997, Stanford, California, MIT Artificial Intelligence Laboratory.
Dhaussy, Philippe, et al., “Global control synthesis for an MIMD/FPGA machine”, © 1994 IEEE, Publ. No. 0-8186-5490-2/94, pp. 72-81.
Elliott, Duncan, et al., “Computational Ram: a memory-SIMD hybrid and its application to DSP”, © 1992 IEEE, Publ. No. 0-7803-0246-X/92, pp. 30.3.1-30.6.4.
Fortes, Jose, et al., “Systolic arrays, a survey of seven projects”, © 1987 IEEE, Publ. No. 0018-9162/87/0700-0091, pp. 91-103.
Gokhale, M., et al., “Processing in Memory: The Terasys Massively Parallel PIM Array” © Apr. 1995, IEEE, pp. 23-31.
Gunther, Bernard, et al., “Assessing Document Relevance with Run-Time Reconfigurable Machines”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 10-17.
Hagiwara, Hiroshi, et al., “A dynamically microprogrammalbe computer with low-level parallelism”, © 1980 IEEE, Publ. No. 0018-9340/80/07000-0577, pp. 577-594.
Hartenstein, R. W., et al. “A General Approach in System Design Integrating Reconfigurable Accelerators,” http:xputers.informatik.uni-kl.de/papers/paper026-1.html, IEEE 1996 Conference, Austin, TX, Oct. 9-11, 1996.
Hartenstein, Reiner, et al., “A reconfigurable data-driven ALU for Xputers”, © 1994 IEEE, Publ. No. 0-8186-5490-2/94, pp. 139-146.
Hauser, John, et al.: “GARP: a MIPS processor with a reconfigurable co-processor”, © 1997 IEEE, Publ. No. 0-08186-8159-4/97, pp. 12-21.
Hayes, John, et al., “A microprocessor-based hypercube, supercomputer”, © 1986 IEEE, Publ. No. 0272-1732/86/1000-0006, pp. 6-17.
Herpel, H. -J., et al., “A Reconfigurable Computer for Embedded Control Applications”, © 1993 IEEE, Publ. No. 0-8186-3890-7/93, pp. 111-120.
Hogl, H., et al., “Enable++: A second generation FPGA processor”, © 1995 IEEE, Publ. No. 0-8186-7086-X/95, pp. 45-53.
King, William, et al., “Using MORRPH in an industrial machine vision system”. © 1996 IEEE, Publ. No. 08186-7548-9/96, pp. 18-26.
Manohar, Swaminathan, et al., “A pragmatic approach to systolic design”, © 1998 IEEE, Publ. No. CH2603-9/88/0000/0463, pp. 463-472.
Mauduit, Nicolas, et al., “Lneuro 1.0: a piece of hardware LEGO for building neural network systems,” © 1992 IEEE, Publ. No. 1045-9227/92, pp. 414-422.
Mirsky, Ethan A., “Coarse-Grain Reconfigurable Computing”, Massachusetts Institute of Technology, Jun. 1996.
Mirsky, Ethan, et al., “MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 157-166.
Morley, Robert E., Jr., et al., “A Massively Parallel Systolic Array Processor System”, © 1988 IEEE, Publ. No. CH2603-9/88/000/0217, pp. 217-225.
Patterson, David, et al., “A case for intelligent DRAM: IRAM”, Hot Chips VIII, Aug. 19-20, 1996, pp. 75-94.
Peterson, Janes, et al., “Scheduling and partitioning ANSI-C programs onto multi-FPGA CCM architectures”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 178-187.
Schmit, Herman, “Incremental reconfiguration for pipelined applications,” © 1997 IEEE, Publ. No. 0-8186-8159-4/97, pp. 47-55.
Sitkoff, Nathan, et al., “Implemen
Ho Andy
Kubida William J.
Martensen Michael C.
SRC Computers, Inc.
Thomson William
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