System and method for controlling voltage and current characteri

Details System and method for controlling voltage and current characteri System and method for controlling voltage and current characteri

1995-08-25

1997-07-29

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

36518518, 36518525, 36518911, G11C 1602

Patent

active

056527225

ABSTRACT:
A memory array has a floating gate transistor cell connected to a bit line and a bit line driver circuit comprising a variable impedance FET and an active load powering the bit line from a supply node. A control circuit selects a voltage applied to the gate of the variable impedance FET to control the bit line voltage, e.g., in dependence on parameters of the cell.

REFERENCES:
patent: 5016218 (1991-05-01), Yamazaki
patent: 5253201 (1993-10-01), Atsumi
patent: 5398203 (1995-03-01), Prickett
patent: 5444656 (1995-08-01), Bauer
patent: 5469384 (1995-11-01), Lacey
Hoff et al., "A 23-ns 256K EPROM with Double-Layer Metal and Address Transition Detection," IEEE Journal of Solid-State Circuits 24:5, Oct., 1989, pp. 1250-1258.

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