Patent
1996-10-10
1999-04-27
Powell, Mark R.
395848, 395849, 395878, 395308, 395555, H04L 704, G06F 1342, G06F 104
Patent
active
058988955
ABSTRACT:
A system and method for providing speed-regulated data transmission between two synchronous systems in different clock domains. A first synchronous circuit includes a memory device, and a second synchronous circuit includes one or more data-requesting devices. The first synchronous circuit operates at a greater clock speed than the clock speed of the second synchronous circuit. A read request buffer queues read request signals from the data-requesting devices, and outputs one of the read request signals to the memory device. A pulse generator receives the read request signal which was output from the queue, and generates a plurality of signal pulses in response thereto. Each of the pulses occurs at a different predetermined time from the occurrence of the read request signal. One of the pulses is selected to be the read acknowledge signal, and assertion of the read acknowledge signal allows the read request buffer queue to output another read request signal.
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Johnson Charles A.
Powell Mark R.
Rossi Jeffrey Allen
Starr Mark T.
Unisys Corporation
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