Pulse or digital communications – Receivers
Reexamination Certificate
2007-07-31
2007-07-31
Tran, Khai (Department: 2611)
Pulse or digital communications
Receivers
C714S795000
Reexamination Certificate
active
09954915
ABSTRACT:
An architecture and method are disclosed for concurrently processing multimedia data from several satellite transponders or satellite carriers. In one embodiment, a combination of a fast Fourier transform, a complex multiplication, and an inverse fast Fourier transform are performed on a group of transponders/carriers to filter the underlying multimedia content, to decimate the signals and to correct for gain and phase imbalances.
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James Tsui, Frequency Channelization, Digital Techniques for Wideband Receivers, Second Edition, pp. 363-396, 2001 Artech House, Inc., Norwood, MA, Dec. 2003.
Zhengdao Wang and Georgios B. Giannakis, Wireless Multicarrier Communications where Fourier Meets Shannon, Department of ECE, University of Minnesota, Minneapolis MN., pp. 1-21, May 2000.
E. Verriest, ISEN, Implementing an Adaptive Noise Canceling System to Enhance Sonar Receiver Performance Using the TMS320C31 DSP, ESIEE, Paris, Sep. 1996, Texas Instruments, pp. 1-24.
G.A. Shaw, R.A. Ford, J.C. Anderson, B.W. Zuerdnorfer, A.H. Anderson, RASSP Benchmark 2 Technical Description, Massachusetts Institute Of Technology Lincoln Library, 153 pages total, Aug. 10, 1995.
“www.inventra.com / inventra / softcore / workshop / MultiRaFiltDes95 /” Mentor Graphics, Hardware Design of Decimators / Interpolators, pp. 1-38, 2006.
“www.mentor.com / inventra / softcore / workshop / SDmod95 /”, Mentor Graphics, Introduction to AD / DA Converters, pp. 1-27, 2006.
http://www.mentor.com/inventra/softcore/workshop/SDHWDes95/ Mentor Graphics, Design of the Decimation & Interpolation Filters, pp. 1-57, 2007.
http://www.mentor.com/inventra/softcore/workshop/Applications95/, Mentor Graphics, Sigma Delta Converter Applications, pp. 1-5, 2007.
Bree, et al., “A Bit-Serial Architecture For A VLSI Viterbi Processor”, Communications Systems Research Group, University of Saskatchewan, Saskatoon, IEEE, WESCANEX '88, 1988, pp. 72-77.
Biver, et al., “Architectural Design and Realization Of A Single-Chip Viterbi Decoder”, Elsevier Science Publishers B.V.,Integration, The VLSI Journal 8 (1989), Oct., No. 1, Amsterdam, NL, pp. 3-16.
Bree, et al., “A Modular Bit-Serial Architecture For Large Constraint-Length Viterbi Decoding”, Communications Systems Research Group, University of Saskatchewan, Saskatoon, Canada, IEEE International Conference on Communications, 1990, pp. 1501-1506.
Choi, et al., “Viterbi Detector Architecture For High-Speed Optical Storage”, 1997, IEEE TENCON—Speech and Image Technologies for Computing and Telecommunications, ASIC Center Corporate Technical Operations SAMSUNG Electronics, vol. 1, Dec. 1997, pp. 89-92.
W.H. Yim and F.P. Coakley, “On-Board Processing For KA-Band Applications”, University of Surrey, UK, Publication Date, Feb. 11, 1993., XP 000458011, pp. 225-229.
Hashida Mitsuyoshi, “Hierachical Network Management System and Control Method for Network Management Information,” Patent Abstracts of Japan, Publication No. 07226777, 2006.
Christensen Kory D.
Digeo, Inc.
Stoel Rives LLP
Tran Khai
LandOfFree
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