Coded data generation or conversion – Converter compensation
Reexamination Certificate
2000-10-24
2002-12-17
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Converter compensation
C341S120000
Reexamination Certificate
active
06496124
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to coder/decoders (codecs) and, more specifically, to a system and method for compensating for codec DC offset through a DC blocking channel and a modem incorporating the same.
BACKGROUND OF THE INVENTION
“56K” modems are currently the most popular means by which users can gain access to the Internet. 56K modems offer users asymmetric connection speeds. For data downloaded from the Internet to the user's modem, a connection speed of over 50 thousand bits per second (kbps) is possible. For data uploaded from the user's modem to the Internet, a maximum connection speed of 28.8 kbps is conventionally possible. The asymmetry is appropriate, because interacting with the Internet almost always results in more data being downloaded than uploaded.
While realizing a higher downloading speed has proven to be challenging, achieving a higher uploading speed is proving to be even more so. One significant problem standing in the way of increasing uploading speed is encountered at a codec employed on the receiving (Internet) end. A codec is employed at the receiving end to digitize the user data symbol stream generated by the modem. Unfortunately, codecs are subject to DC offset at their analog input when the user data symbol stream averages out to a nonzero voltage over time (which is almost always the case). Though codecs are provided with zero balancing circuits, DC offset often changes over time. Zero balancing circuits have proven to be unable reliably to compensate for time-varying DC offsets.
Compensating for DC offset is relatively straightforward if the codec in question is produces a linear digital output; the codec's digital output can be incremented or decremented by a number corresponding to the DC offset. However, codecs often nonlinearly compress their digital output according to well-known A-law or &mgr;-law compression techniques. DC offset does not evidence itself linearly in the output of these codecs, which renders linear DC offset compensation inadequate. Nonlinear digital compensation, while possible, is complex and difficult to implement.
It would, of course, be desirable simply to bias the user data symbol stream with a DC component to compensate for DC offset at the receiving codec. However, in the case of 56k modems, the transmission path, or channel, connecting the modem to the codec contains a DC blocking device. The DC blocking device, which usually takes the form of a transformer would serve to block any DC component before it could reach the codec and compensate for DC offset.
Accordingly, what is needed in the art is a way to compensate for codec DC offset that is compatible with DC blocking channels.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a system for, and method of, compensating for codec DC offset and a modem incorporating the system or the method. In one embodiment, the system includes: (1) a DC offset compensator that develops and transmits a DC offset indicator signal corresponding to a DC offset present along a transmission path to a receiving codec and (2) a DC offset encoder, coupled to the DC offset compensator, that receives the DC offset indicator signal and applies a time-varying DC offset compensating signal based thereon to a user data symbol stream transmitted along the transmission path. The DC offset compensator can employ the DC offset compensating signal to remove at least a portion of the DC offset compensating signal to yield the user data symbol stream.
The present invention therefore introduces the broad concept of encoding compensation for codec DC offset in a deterministic, time-varying signal that is transmitted along with a user data symbol stream. Thus, the DC offset is, in effect, encoded into AC form.
The time-varying signal can traverse any DC blocking circuitry, such as a transformer, and thereby reach the receiving codec. Because the time-varying signal is deterministic, circuitry proximate the receiving codec can compute and remove the time-varying signal, leaving the user data symbol stream for digitization.
In one embodiment of the present invention, the DC offset compensating signal comprises a deterministic pseudo-random number sequence. Those skilled in the pertinent art are familiar with pseudo-random numbers and techniques for generating them. The present invention can make use of such techniques to generate the same pseudo-random number sequence at both the transmitting and receiving ends of a communications channel. The pseudo-random number sequence is first added to, and then subtracted from, a user data symbol stream to compensate for DC offset that may occur due to patterns in the user data symbol stream.
In one embodiment of the present invention, the DC offset compensating signal has a component that tends to average about an oppositely signed negative of the DC offset. In an embodiment to be illustrated and described, if the DC offset is represented by C, the component of the DC offset compensating signal tends to average about −C.
In one embodiment of the present invention, the DC offset compensator removes an entirety of the DC offset compensating signal. This maximizes compensation for DC offset. However, in some embodiments of the present invention, some portion of the DC offset compensating signal may, or may be allowed to, remain. In the broad scope of the present invention, at least some DC offset compensation occurs.
In one embodiment of the present invention, the DC offset compensator removes at least the portion of the DC offset compensating signal by recalculating the pseudo-random number sequence. Recalculation allows the pseudo-random number sequence to be at least partially removed from any user data symbol stream.
In one embodiment of the present invention, the DC offset compensating signal is capable of passing substantially undistorted through a DC blocking transformer. In an alternative embodiment of the present invention, the DC offset indicator signal may be somewhat distorted (or attenuated), but DC offset compensation still at least partially takes place by virtue of its presence.
In one embodiment of the present invention, the DC offset encoder is associated with a 56K modem. Those skilled in the pertinent art will appreciate that compensation for any DC offset that may occur at the receiving codec allows for higher upstream communication rates with such modems. Those skilled in the pertinent art will also understand that the principles of the present invention may be broadly applied in a variety of circumstances in which a DC signal is required to be encoded into AC form for the purpose of traversing a DC blocking circuit.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
REFERENCES:
patent: 5999109 (1999-12-01), Norrell et al.
patent: 6278744 (2001-08-01), Olafsson et al.
patent: 6289070 (2001-09-01), Krone et al.
Agere Systems Guardian Corp.
Williams Howard L.
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