Communications: electrical – Digital comparator systems
Reexamination Certificate
1999-08-31
2001-02-20
Wambach, Margaret R. (Department: 2816)
Communications: electrical
Digital comparator systems
C326S040000
Reexamination Certificate
active
06191683
ABSTRACT:
TECHNICAL FIELD
The present invention is generally related to the fields of computers and digital analysis and, more particularly, is related to a system and method for comparing values from a target system during logic analysis.
BACKGROUND OF THE INVENTION
Current manufacturers of high-speed computer equipment often need to access data information that is communicated on a data bus or other conductors within the equipment for testing or other reasons. Conventional approaches to accessing data on a bus include the use of logic analyzers that provide probes that are placed in electrical contact with the particular conductors in question.
In a typical arrangement, the probes are positioned to obtain the data signals from the target system and the target system is operated to produce the desired data values that are captured by the probes. These data values are acquired and stored in a memory in the logic analyzer. However, many of the target systems that are analyzed using logic analyzers operate at speeds measured in hundreds of megahertz. Consequently, the data values obtained from such a target system will quickly fill up the memory of the logic analyzer. In many cases, this occurs within a few milliseconds.
As a result, logic analyzers have employed circuitry to perform a quick comparison between the values obtained from the target system and desired values specified by the user to detect specific data values from the target system. Generally, only those data values from the target system are stored in the memory of the logic analyzer. In this manner, a reduced number of data values are then stored in the memory of the logic analyzer, thus preventing the memory from becoming full prematurely.
The approaches employed to perform this comparison typically employ logic circuits and other devices of significant size and complexity. Accordingly, such circuits are costly and the number of desired values that may be employed by a single logic analyzer are limited.
SUMMARY OF THE INVENTION
In light of the foregoing, the present invention provides for a system and method to compare logical values from target systems. In one embodiment, the system employs a field programmable gate array (FPGA) configured for comparing logical values. In this embodiment, the FPGA includes a number of inputs to receive an N-bit logical value from a target system, where N defines the number of bits in the N-bit logical value. The FPGA also includes a number of lookup tables configured to receive an M-bit portion of the N-bit sampled value. These lookup tables generate a lookup table output in response to the M-bit portion. Finally, a logical AND operation is performed on the outputs of the lookup tables that generates an output indicating whether the particular N-bit logical value matches a particular desired value. Note that a single AND gate may be used or a number of AND gates may be used in place of the single AND gate. In this embodiment, the tables within the lookup tables are generated based upon a desired logical value and a comparison mask value.
The present invention may also be viewed as a method for compare logical values. In one embodiment, this method employs a field programmable gate array, comprising the steps of: receiving an N-bit logical value, where N defines the number of bits in the N-bit logical value, matching a number of M-bit portions of the N-bit sampled value with one of a number of M-bit portion variations, wherein a matching output is generated depending upon the M-bit portion variation that matches the M-bit portion, and, performing an AND operation on all of the matching outputs.
The various embodiments of the present invention provide a significant advantage in that a single FPGA may be employed to perform a greater number of comparisons than prior art configurations. Thus, a logic analyzer that employs the present invention has much greater capacity to detect specific logical values from a target system.
REFERENCES:
patent: 4100532 (1978-07-01), Farnbach
Agilent Technologie,s Inc.
Wambach Margaret R.
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