System and method for compacting integrated circuit layouts

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364489, 364488, 364490, G06F 1560

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active

054167221

ABSTRACT:
A computer aided design process for compacting semiconductor circuit layouts to meet a specified set of design rules begins by fracturing a specified circuit layout into a maximal set of trapezoids and storing the resulting trapezoidal cells in a database that denotes the boundaries of each cell, and the cell adjacent to each boundary. Empty spaces between cells are represented by additional cells. For each cell boundary, the database also stores data representing the boundary edge's end points. Neighboring cells on the same and related layers of the circuit layout share edges in the database. When an edge of a cell is moved, the shared edge of each neighboring cell is implicitly moved because it uses the same edge data. To adjust a circuit layout, the cells in the layout are processed in sorted order. For each cell, a set of width and spacing design rules are applied to the bottom and top edges of the cell which may result in movement of the cell and adjustment of the cell's width. An adjacent cell adjustment process conforms adjacent cells to the boundary movements of other cells. The compaction process is performed once for X-direction compaction and once for Y-direction compaction. The compaction process is computationally efficient because each cell is linked by the database to its adjacent cells, virtually eliminating the need to search through cells not needed for each design rule check, and because movement of one cell's edges automatically adjusts adjacent cells via their shared edges.

REFERENCES:
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patent: 5281558 (1994-01-01), Bamji et al.
patent: 5309371 (1994-05-01), Shikata et al.
patent: 5315534 (1994-05-01), Schlachet
"Compaction Based Custom LSI Layout Design Method" by Ishikawa et al., IEEE Computer Society Press, 1985, pp. 343-345.

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