Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2007-11-27
2007-11-27
Kindred, Alford (Department: 2181)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S028000, C712S032000, C712S034000, C712S203000
Reexamination Certificate
active
10174716
ABSTRACT:
A method for communicating in a multi-processor environment is provided that includes generating a bit at an originating processor associated with a message to be communicated to a destination processor. The bit is positioned in a send register associated with the originating processor and transposed from the send register of the originating processor to a receive register of the destination processor. An interrupt signal is then generated in response to the bit being transposed.
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Garner Trevor S.
King Robert L.
Lee William R.
Mitten John W.
Baker & Botts L.L.P.
Cisco Technology Inc.
Kindred Alford
Moll Jesse R
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