System and method for common mode bias for high frequency...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Nonlinear amplifying circuit

Reexamination Certificate

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Details

C327S108000, C327S562000

Reexamination Certificate

active

07733167

ABSTRACT:
Methods and systems for reducing parasitic capacitance of a buffer for an electric circuit are disclosed and may include coupling a gate of a first transistor to a first differential input of the buffer via a first capacitor, coupling a gate of a second transistor to a second differential input of the buffer via a second capacitor. The first and second transistors may be biased by a common mode output of a direct current (DC) voltage source for the buffer. The common mode output of the DC voltage source may be directly coupled to at least one differential output of the buffer via an inductor. The first transistor and the second transistor may comprise NMOS transistors and/or PMOS transistors. The DC voltage source may comprise a PMOS transistor and/or an NMOS transistor.

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