System and method for common mode bias for high frequency...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Nonlinear amplifying circuit

Reexamination Certificate

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C327S562000, C327S108000

Reexamination Certificate

active

10976996

ABSTRACT:
Methods and systems for reducing parasitic capacitance of a buffer for an electric circuit are disclosed herein. Aspects of the method may comprise coupling a gate of a first transistor to a first differential input of the buffer and coupling a gate of a second transistor to a second differential input of the buffer. The first and second transistors may be biased by a common mode output of a direct current (DC) voltage source for the buffer, where the common mode output of the DC voltage source may be coupled to the gate of the first transistor and the gate of the second transistor. The first transistor and the second transistor may comprise NMOS transistors and/or PMOS transistors. The DC voltage source may comprise a PMOS transistor and/or an NMOS transistor.

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patent: 6281749 (2001-08-01), Klayman et al.
patent: 6583661 (2003-06-01), Tanji et al.
patent: 6882218 (2005-04-01), Gupta
patent: 7071779 (2006-07-01), Shi et al.
patent: 7095272 (2006-08-01), Morishita
patent: 2004/0160268 (2004-08-01), Ozasa et al.
patent: 2005/0046472 (2005-03-01), Kim
patent: 2005/0073352 (2005-04-01), Behzad

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