System and method for coarse tuning a phase locked loop...

Details System and method for coarse tuning a phase locked loop... System and method for coarse tuning a phase locked loop...

2003-02-14

2004-08-10

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

C331S00100A, C331S010000, C331S014000, C331S016000

Reexamination Certificate

active

06774732

ABSTRACT:

TECHNICAL FIELD
This invention relates in general to phase locked loops (PLL) and more particularly to the tuning of a voltage controlled oscillator (VCO) to stay within the operational range of a PLL synthesizer.
BACKGROUND
The use of a voltage controlled oscillator (VCO) in phased locked loop (PLL) designs are well known in the art and are used in many different types of radio frequency (RF) industrial and consumer electronic circuit applications. Typically a PLL is used to control the VCO in order to provide a highly stable source of RF energy preferably with low current drain. One problem associated in using a voltage controlled oscillator (VCO) is that there are many different types of factors that work to change and/or vary the oscillators center frequency of operation. These factors include variations in VCO components, power supply restrictions that limit the dynamic range of the PLL and a need to lower the VCO frequency gain limiting PLL range. Many environmental conditions also contribute vary center frequency such as wide swings in ambient temperature. Often these deviations in center frequency can be extreme to the extent that the PLL will no longer operate due to this frequency deviation and the PLL's design limitations.
In addition, modern wireless networked devices require low cost implementations and demand quick methods to tune the range of the integrated VCO. These methods are often required to be as simple as possible to reduce the cost of implementing the integrated VCO in a device. The time required to “tune” is important to reduce power dissipation and overall current drain in the device. The longer the device has to be in the “operational” state the greater the average current drain. In a wireless network such as that defined by the Institute of Electrical and Electronics Engineers IEEE 802.15.4 WPAN standard, low power consumption is crucial. Hence, any modern VCO tuning method for wireless networked devices should be low in complexity with rapid speed in tuning.
FIG. 1
illustrates a prior art circuit diagram of a commonly used phase-frequency detector (PFD) circuit
100
. Although there are many alternative PFD circuit designs, a configuration that includes two flip-flops and an AND gate is the most common and depicted here by way of example. The PFD
100
utilizes a plurality of flip-flops (
101
,
103
,
105
,
107
) to compare the phase of a first input
111
and a second input
113
. The PFD
100
then determines whether the operational frequency of input signals needs to be increased or decreased to match the phase of these input signals. This information is output at the up output
115
and output
117
.
As is well known in the art, PFD
100
offers some unique benefits if the signals input to input
111
and input
113
are substantially distinct in frequency and phase. If the signals that are directed to input
111
and input
113
are greater than 360 degrees (2-pi or 2&pgr; radians) out of phase, then PFD
100
offers the ability to provide a phase slip. As known in the art, a “phase slip” is the ability to detect a required amount of frequency correction that should be applied to keep the two input signals in-phase. Flip flop
105
and flip flop
107
as well as the OR gate
119
provide an ability to measure this phase slip.
Hence, PFD
100
provides the ability to determine whether there are two “UP” frequency corrections before there is a “DOWN” frequency correction or alternatively whether there are two “DOWN” frequency corrections before there is an “UP” frequency correction. When this occurs PFD
100
can determine with certainty that the signals provided to the inputs
111
,
113
are more than 360 degrees out of phase. If the two input signals are too low in frequency, there will be a high pulse on the UP-SLIP output
121
. Conversely if the two input signals are too high in frequency, there will be a high pulse generated on the DOWN-SLIP output
123
. The OR gate
119
is used to remove the pulse once it is provided to either the UP-SLIP output
121
or DOWN-SLIP output
123
. As will be evident to those skilled in the art, PFD
100
is used to provide a direction upon which to make a frequency correction. U.S. Pat. No. 4,764,737 assigned to Motorola, Inc. describes this invention in detail and is herein incorporated by reference.
Prior art techniques for tuning a VCO have used a “closed loop” operation of the PLL to extract information in order to make decisions on the VCO's range of operation. For example, U.S. Pat. No. 5,686,864 assigned to Motorola, Inc. entitled “Method and Apparatus for Controlling a Voltage Controlled Oscillator Tuning Range in a frequency Synthesizer” determines shift based on the control voltage level of the VCO. One disadvantage of using this type of technique is the closed loop operation range of the control VCO control voltage range will be limited by the levels set by the “lock detect” circuitry. Still another disadvantage are large time constants involved with making this determination. Since the PLL operates closed loop, the time constants can be very large. This has the effect of limiting the minimum time to “tune” the VCO.
Further, there are additional patents that use a closed loop operation to tune the range of the VCO. U.S. Pat. No. 5,736,904 assigned to Motorola, Inc. entitled “Automatic trimming of a controlled Oscillator in a Phase Locked Loop,” and herein incorporated by reference illustrates this type of tuning operation. This type of technique increases system complexity by incorporating analog-to-digital converters (A/Ds) and digital-t-analog converters (D/As) as a method to store tuning values. U.S. Pat. No. 5,389,898 also assigned to Motorola, Inc. entitled “Phase Locked Loop having plural Selectable Voltage Controlled Oscillators” also operates with the PLL in a closed loop operation. These types of systems require that the VCOs have a non-overlapping range.
Thus, the need exists to provide a PLL synthesizer and method that places less restriction on the VCOs overlapping range. The PLL synthesizer should be low cost, fast acting that should enable the free running frequency of a VCO to be coarsely tuned to stay within a predetermined range.
SUMMARY OF THE INVENTION
Briefly, according to the invention, there is provided a system and method for coarse tuning the voltage controlled oscillator (VCO) in a phase locked loop (PLL) synthesizer. During a coarse tune mode, the voltage on the VCO input is forced to a predetermined nominal value by removing the charge pump from the PLL circuit and setting a desirable target bias for the VCO free running frequency. The circuit topology of the present invention uses a loop filter driven by the same voltage reference that also drives the input to the VCO. This has the effect of minimizing transients and settling the frequency of operation when the PLL switches from a “coarse tune” mode to normal closed loop tracking mode. The output of the VCO is compared to the reference frequency after a pre-determined frequency division. The phase detector is designed to output pulses whenever a 2&pgr; slip occurs between the reference frequency and the divided down VCO. The 2&pgr; slip pulses are used by a monitor and control circuit to estimate the error in the VCO's operating center frequency. The invention provides several methods by which to monitor and control is frequency. The output of the monitor and control circuit can then be used to control a second port in the VCO that acts to coarse tune the VCO without affecting its tune sensitivity. The present invention offers a distinct advantage in that the coarse tuning system does not require the closed loop operation of the PLL. Thus, the PLL quickly arrives at a final frequency adjustment solution, and can be used with VCOs that have overlapping and non-monotonic tune ranges.


REFERENCES:
patent: 5389898 (1995-02-01), Taketoshi et al.
patent: 5686864 (1997-11-01), Martin et al.
patent: 5736904 (1998-04-01), Humphreys et al.
patent: 5783972 (1998-07-01), Nishikawa
patent: 6256362 (2001-07-01)

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