System and method for check-in control in wafer testing

Details System and method for check-in control in wafer testing System and method for check-in control in wafer testing

2006-10-17

2006-10-17

Hollington, Jermele (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

07123040

ABSTRACT:
A testing system for check-in control in wafer testing. The testing system comprises a testing tool, an optical character recognition (OCR) device, and a controller. The testing tool performs a testing process of an article. The OCR device reads optical characters disposed on the article. The controller, connected to the testing tool and the OCR device, automatically initiates a check-in process for the article according to the read optical characters.

REFERENCES:
patent: 6072325 (2000-06-01), Sano
patent: 6097204 (2000-08-01), Tanaka et al.
patent: 6111421 (2000-08-01), Takahashi et al.
patent: 6684125 (2004-01-01), Kahn et al.
patent: 6862495 (2005-03-01), Kahn et al.
patent: 6937753 (2005-08-01), O'Dell et al.
patent: 2004/0234362 (2004-11-01), Iijima et al.
patent: 10090367 (1998-04-01), None

Affiliated with

Also associated with

Rating

System and method for check-in control in wafer testing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for check-in control in wafer testing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for check-in control in wafer testing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3717999