Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system
Reexamination Certificate
2011-06-07
2011-06-07
Shah, Kamini S (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
C703S002000, C703S022000, C702S176000, C702S179000, C702S186000, C702S187000, C702S188000, C710S018000, C717S103000
Reexamination Certificate
active
07957948
ABSTRACT:
A method for expressing a hierarchy of scalabilities in complex systems, including a discrete event simulation and an analytic model, for analysis and prediction of the performance of multi-chip, multi-core, multi-threaded computer processors is provided. Further provided is a capacity planning tool for migrating data center systems from a source configuration which may include source systems with multithreaded, multicore, multichip central processing units to a destination configuration which may include destination systems with multithreaded, multicore and multichip central processing units, wherein the destination systems may be different than the source systems. Apparatus and methods are taught for the assembling of and utilization of linear and exponential scalability factors in the capacity planning tool when a plurality of active processor threads populate processors with multiple chips, multiple cores per chip and multiple threads per core.
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Neuse Douglas M.
Walton Christopher B.
Zink Kenneth C.
Hyperformit, Inc.
Patel Shambhavi
Schultz & Associates P.C.
Shah Kamini S
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