System and method for calibrating damping factor or analog PLL

Details System and method for calibrating damping factor or analog PLL System and method for calibrating damping factor or analog PLL

1996-05-13

1997-09-16

Pascal, Robert

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 16, 331 17, 331 25, 331 44, 327157, 327159, H03L 7089

Patent

active

056685033

ABSTRACT:
Calibration systems and techniques for analog phase-lock loops (PLLs) providing the capability to dynamically maintain a constant damping factor. Damping factor is calibrated by automatically setting a reference bias current I.sub.r to the PLL's charge pump such that the charge current I.sub.c output therefrom maintains the desired PLL damping characteristic. The technique presented involves selecting a known first frequency F.sub.1 and allowing the PLL circuit to reach steady state, after which a known second frequency F.sub.2 is applied and the PLL circuit is monitored to determine whether steady state at this second frequency F.sub.2 is accomplished within a predetermined target time T.sub.x, which corresponds to the desired damping factor. The determination of whether lock occurs within the target time T.sub.x is then employed to automatically setting the reference current I.sub.r.

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