Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
1999-07-12
2001-05-15
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S162000
Reexamination Certificate
active
06232897
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the art of analog-to-digital (A/D) converters, and more particularly, to A/D converters which include linearity errors.
DESCRIPTION OF THE RELATED ART
Analog-to-digital converters (ADCs) are circuits used to convert signals from the analog domain, where the signals are represented by continuous quantities such as voltage and current, to the digital domain, where the signals are represented by numbers. These circuits can be implemented in a large number of ways. Established A/D conversion techniques include flash, delta-sigma (or sigma-delta), sub-ranging, successive approximation, and integrating.
One example of an A/D converter is an over-sampled A/D converter. Oversampled A/D converters, often denoted as “delta-sigma converters” or “sigma-delta converters” are well known in the art. Delta-sigma (D/S) converters have gained in popularity due primarily to their ability to realize high resolution analog-to-digital conversion in mixed signal VLSI processors.
A D/S converter essentially digitizes an analog signal at a very high sampling rate (oversampling) in order to perform a noise shaping function. Digital filtering after the noise shaping allows the D/S converter to achieve a high resolution when compared with conventional A/D converters. Decimation is thereafter used to reduce the effective sampling rate back to the “Nyquist” rate. To gain an understanding of D/S converters, it is important to understand the operation of oversampling, noise shaping, digital filtering and decimation, the key concepts involved.
FIG. 1
shows, in block diagram form, a single bit D/S converter
10
commonly known in the art. The single bit D/S converter
10
includes a single bit D/S modulator
12
connected to a digital filter and decimation circuit
14
. The D/S modulator
12
includes a summing node
16
, a filter
18
, a single bit A/D converter
20
, and a single bit D/A converter
22
. The D/A converter
22
is connected to the output of the A/D converter
20
and operates to provide feedback to the summing node
16
. The summing node
16
includes a pair of inputs, one being connected to the analog input signal V
in
and the other being connected to the output of the D/A converter
22
.
In operation, the output of summing node
16
is low-pass filtered by filter
18
and subsequently converted into a single bit, digital signal by A/D converter
20
. The single bit digital signal in turn is converted back into an analog signal by D/A converter
22
and subtracted from analog input signal V
in
at summing node
16
.
The single bit D/S modulator
12
converts the input signal V
in
into a continuous serial stream of 1s and 0s at a rate determined by sampling clock frequency, kf
s
. Due to the feedback provided by the D/A converter
22
the average value output by the D/A converter
22
approaches that of the input signal V
in
if the loop has enough gain.
FIG. 2A
shows a schematic implementation of the single bit D/S converter of FIG.
1
. In particular,
FIG. 2A
shows a single bit D/S converter
30
which includes a single bit D/S modulator
32
connected to a digital filter and decimation circuit
34
. The single bit D/S modulator
32
includes a summing node
36
, an integrator
38
, a latched comparator
40
which functions as the single bit A/D converter, and a simple switching mode device
42
which finctions as the single bit D/A converter.
Integrator
38
acts as a filter and has an amplitude response in the frequency domain proportional to 1/f, where f is the input frequency. Since the chopper like action of the clocked, latched comparator
40
converts the input signal to a high frequency AC signal, varying about the average value of the input V
in
, the effective quantization noise at low frequencies is greatly reduced. In effect, low frequency quantization noise is “shaped” into higher frequencies.
FIG. 2B
shows the simulated noise density as a function of frequency of a D/S modulator. The y-axis is in dB and the x axis is in MHz. As can be seen, the lower noise frequencies are attenuated. The exact frequency spectrum of the resulting noise shaping depends on the sampling rate, the integrator time constant, and the order of the filter.
Clearly, a single bit, digital representation of an analog signal has very little resolution. The D/S modulator
32
of
FIG. 2A
is very difficult to analyze in the time domain because of the apparent randomness of the single bit nature of the data. For any given input value in a single sampling interval, data from the latched comparator
40
is virtually meaningless. A meaningful value results only when a large number of samples are averaged. If the input signal V
in
is near positive full scale, it is clear that there will be more 1s than 0s in the bit stream. Likewise, for signals near the negative full scale, there will be more 0s than is in the bit stream. For input signals near the midscale, there will be approximately an equal number of 1s and 0s.
After the quantization noise has been shaped by the D/S modulator
32
, the output of the D/S converter
30
is further processed by the digital filter and decimator circuit
34
. The purpose of the digital filter is two fold. First, the digital filter acts as an anti-aliasing filter with respect to the final sampling rate, fs. Second, the digital filter filters out the higher frequency noise produced by the noise shaping process of the D/S modulator
32
. Final data reduction is performed by digitally resampling the filtered output using a process called decimation. Decimation is the process of resampling at a lower rate. Decimation can be viewed as the method by which redundant signal information introduced by the oversampling process is removed.
FIG. 3
shows a multi-bit D/S converter
50
in block diagram form. The multi-bit D/S converter
50
includes a multi-bit D/S modulator
52
connected to a multi-bit digital filter and decimation circuit
54
. The multi-bit D/S modulator
52
further includes a summing node
56
, a filter
58
, a multi-bit AID converter
60
, and a multi-bit internal D/A converter
62
.
The multi-bit D/S modulator
50
of
FIG. 3
operates similarly to the single-bit D/S converter of FIG.
1
. The output of the summing node
56
is low-pass filtered by filter
58
and converted into a multi-bit digital signal by multi-bit internal A/D converter
60
operating at oversampling rate kf
s
. The multi-bit D/A converter
62
is connected via a feedback loop between the output of the multi-bit A/D converter
60
and an input node of the summing node
56
, whereby the analog signal output of the D/A converter
62
is subtracted from the analog signal input V
in
. Again, the output of D/A converter
62
approaches that of the analog input signal V
in
due to the feedback involved. Digital filter and decimation circuit
54
removes quantization noise shaped into the higher frequencies and resamples the oversampled digital signal at rate f
s
.
The multi-bit D/S converter
50
of
FIG. 3
provides benefits over the single bit D/S converter
10
of FIG.
1
. Namely, the multi-bit D/S converter
50
provides more resolution and less quantization noise. Additionally, the multi-bit D/S converter
50
is more stable than single bit D/S converters. However, the multi-bit D/S converter suffers from linearity errors introduced by the internal multi-bit D/A converter
62
. Single bit D/S converters on the other hand do not produce linearity errors.
Linearity error is the inability of the multi-bit D/A converter to accurately translate a digital input value into an analog current or voltage. In other words, given a particular digital input, the resulting analog output of the multi-bit internal D/A converter
62
approximates the digital value but is not exactly equal to the digital value. In reality, the actual analog output differs from the digital input value by an amount equal to the linearity error.
FIG. 4
shows a graphical comparison of an ideal linear vs. non-ideal, non-linear multi-bit D/A converter. The horizontal axis represents
Cho James H.
Conley Rose & Tayon PC
Hood Jeffrey C.
National Instruments Corporation
Tokar Michael
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