System and method for buffering multiple frames while controllin

Details System and method for buffering multiple frames while controllin System and method for buffering multiple frames while controllin

1996-11-06

1999-08-03

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

345501, G06F 1300

Patent

active

059331550

ABSTRACT:
A system and method for managing multiple frame buffers. The system includes multiple frame buffers, and thus reduces the risk of dropped frames. The system controls and bounds render-to-display latency, and provides an application friendly and effective interface to the frame buffers. The system operates by estimating a latency of a frame that is yet to be rendered. The system determines whether the latency is greater than a target latency. If the latency is greater than the target latency, then the system blocks the application that is responsible for rendering the frame before rendering of the frame commences. As a result, render-to-display latency is bounded to the target latency. The system addresses the naming issue by providing the application with access to only the front buffer and the back buffer. In particular, the present system maintains a queue of one or more frame buffers. The newest frame buffer appended to the queue is considered to be the front buffer. The oldest frame buffer in the queue is displayed. A frame buffer not in the queue is considered to be the back buffer. Rendering is enabled to the back buffer. Once rendering to the back buffer is complete, the back buffer is appended to the queue and becomes the new front buffer.

REFERENCES:
patent: 5519825 (1996-05-01), Naughton et al.
patent: 5617118 (1997-04-01), Thompson

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