System and method for bit timing synchronization in an adaptive

Details System and method for bit timing synchronization in an adaptive System and method for bit timing synchronization in an adaptive

1993-06-04

1994-03-22

Cain, David C.

Pulse or digital communications

Repeaters

Testing

380 48, 380 49, H04L 900

Patent

active

052971627

ABSTRACT:
In a CDMA communication system (100) capable of communicating between a receiver (20) and a transmitter (10) direct sequence spread spectrum communication signals (30), a system and method for synchronizing receiver bit timing and transmitter timing. Transmitter (10) transmits a training bit sequence (31) followed by a transmitter bit timing sequence (33). The receiver (20) adaptively determines a representation of a despreading chip sequence using a tapped delay line equalizer (400). Receiver bit timing offset is determined based on the representation of the despreading chip sequence and the transmitter bit timing sequence (33).

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Madhow, U., Honig, M. L., "Minimum Mean Squared Error Interference Suppression for Direct Sequence Spread-Spectrum Code-Division Multiple-Access," Proceeding of the 1st Intl. Conf. on Universal Personal Communication, Dallas, Sep. 1992.
Madhow, U., Honig, M. L., Bell Communications Research, "Error Probability and Near-Far Resistance of Minimum Mean Squared Error Interference Suppression Schemes for CDMA," IEEE, #0-7803-0608, Feb. 1992, pp. 1339-1343.
Cook, C. E., Marsh, H. S., "An Introduction to Spread Spectrum," IEEE #0163-6804-83/-300-0008, Mar. 1983, pp. 8-16.

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