Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2002-12-20
2004-02-17
Jung, Min (Department: 2661)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C714S751000
Reexamination Certificate
active
06693910
ABSTRACT:
FIELD OF INVENTION
The present invention is related to communication systems which use a hybrid automatic repeat request (H-ARQ) scheme for improving quality of service, (e.g. system throughput). More particularly, the present invention is directed to a system and method for reducing the latency of the H-ARQ reordering buffers within a receiver.
BACKGROUND
H-ARQ processing is a scheme comprising multiple parallel ARQ processors whereby each processor repeatedly transmits several sequential attempts of a data block until the transmission is successful to ensure that each block of data is received without an error. Referring to
FIG. 1
, a simplified flow diagram of the data flow between a Node B (shown at the bottom of
FIG. 1
) and a UE (shown at the top of
FIG. 1
) is shown. Protocol data units from higher level processing are scheduled and may be multiplexed into one data block. A data block can only contain protocol data units of higher layers of the same priority. A unique Transmission Sequence Number (TSN) is assigned to each data block by the scheduler. The higher layers may provide a plurality of streams of different priorities of protocol data units, each priority having a sequence of TSNs. The scheduler then dispatches the blocks to the plurality of H-ARQ processors P
1
B
-P
5
B
. Each H-ARQ processor P
1
B
-P
5
B
is responsible for processing a single block of data at a time. For example, as shown in
FIG. 1
, the Priority
1
protocol data units comprise a sequence illustrated as B
1
1
-B
1
N
. Likewise, the Priority
2
protocol data units are sequenced from B
2
1
-B
2
N
and the Priority
3
protocol data units are sequenced from B
3
1
-B
3
N
. These protocol data units are scheduled (and may be multiplexed) and affixed a TSN by the common scheduler. For purposes of describing the invention, we assume one protocol data unit for one data block. After a data block is scheduled to be processed by a particular processor P
1
B
-P
5
B
, each data block is associated with a processor identifier, which identifies the processor P
1
B
-P
5
B
that processes the data block. It should be understood by those of skill in the art that this association may include “tagging” the data block or may comprise control channel signaling, whereby a control channel provides signaling from the Node B to the UE that a particular data block is associated with a particular transmit processor P
1
B
-P
5
B
. The data blocks are then input into the scheduled Node B H-ARQ processors P
1
B
-P
5
B
which receive and process each data block. Each Node B H-ARQ processor P
1
B
-P
5
B
corresponds to an H-ARQ processor P
1
UE
-P
5
UE
within the UE. Accordingly, the first H-ARQ processor P
1
B
in the Node B communicates with the first H-ARQ processor P
1
UE
in the UE. Likewise, the second H-ARQ processor P
2
B
in the Node B communicates with the second H-ARQ processor P
2
UE
in the UE, and so on for the remaining H-ARQ processors P
3
B
-P
5
B
in the Node B and their counterpart H-ARQ processors P
3
UE
-P
5
UE
respectively within the UE. The H-ARQ processes are timely multiplexed onto the air interface and there is only one transmission of an H-ARQ on the air interface at one time.
For example, taking the first pair of communicating H-ARQ processors P
1
B
and P
1
UE
, the H-ARQ processor P
1
B
processes a data block, for example B
1
1
, and forwards it for multiplexing and transmitting it over the air interface. When this data block B
1
1
is received by the first H-ARQ processor P
1
UE
, the processor P
1
UE
determines whether or not it was received without error. If the data block B
1
1
was received without error, the first H-ARQ processor P
1
UE
transmits an acknowledgment (ACK) to indicate to the transmitting H-ARQ processor P
1
B
that it has been successfully received. On the contrary, if there is an error in the received data block B
1
1
, the receiving H-ARQ processor P
1
UE
transmits a negative acknowledgment (NACK) to the transmitting H-ARQ processor P
1
B
. This process continues until the transmitting processor P
1
B
receives an ACK for the data block B
1
1
. Once an ACK is received, that processor P
1
B
is “released” for processing another data block. The scheduler will assign the processor P
1
B
another data block if available.
As graphically illustrated in
FIG. 1
, the scheduler knows of the release of the processor P
1
B
by receiving the ACK/NACK, or may use some other signaling scheme that is well known in the art.
Once the receiving H-ARQ processors P
1
UE
-P
5
UE
process each data block, they are forwarded to the reordering buffers R
1
, R
2
, R
3
based on their priority; one reordering buffer for each priority level of data. For example, Priority
1
data block B
1
1
-B
1
N
will be received and reordered in the Priority
1
reordering buffer R
1
; Priority
2
data blocks B
2
1
-B
2
N
will be received and reordered in the Priority
2
reordering buffer R
2
; and the Priority
3
data blocks B
3
1
-B
3
N
will be received and reordered by the Priority
3
reordering buffer R
3
. Due to the pre-processing of the data blocks by the receiving H-ARQ processors P
1
UE
-P
5
UE
and the ACK/NACK acknowledgement procedure, the data blocks are often received in an order that is not sequential with respect to their TSNs. The reordering buffers R
1
-R
3
receive the out-of-sequence data blocks and attempt to reorder the data blocks in a sequential manner prior to forwarding onto the RLC layer. For example, the Priority
1
reordering buffer R
1
receives and reorders the first four Priority
1
data blocks B
1
1
-B
1
4
. As the data blocks are received and reordered, they will be passed to the RLC layer.
On the receiving side, the UE MAC-hs, (which has been graphically illustrated as MAC-hs control), reads the H-ARQ processor ID, whether it is sent on a control channel such as the HS-SCCH or whether the data block has been tagged, to determine which H-ARQ processor P
1
UE
-P
5
UE
has been used. If the UE receives another data block to be processed by the same H-ARQ processor P
1
UE
-P
5
UE
, the UE knows that that particular H-ARQ processor P
1
UE
-P
5
UE
has been released regardless of whether or not the previous data block processed by that H-ARQ processor P
1
UE
-P
5
UE
has been successfully received or not.
This process has several drawbacks that can cause a reordering buffer to “stall;” whereby the reordering buffer continues to wait for a data block which may never be transmitted. For example, referring to the Priority
2
reordering buffer R
2
, the third data block B
2
3
is missing. Using the current process, the reordering buffer R
2
will initiate a timer when the subsequent data block B
2
4
is received. The reordering buffer R
2
will wait a predetermined duration as set by the timer to receive the missing data block B
2
3
until the timer “times out.” If it does not receive that data block after the “time out,” it forwards the data blocks B
2
1
-B
2
4
, as well as subsequent data blocks up to the first missing data block, to the RLC layer. The RLC layer can then perform higher level processing to recover the missed data block.
There are several scenarios which increase the probability of reorder buffer stalling. For example, there are scenarios that data blocks of higher priority preempt data blocks of lower priority in H-ARQ transmissions; in this case, a H-ARQ process is released to serve a data block of higher priority regardless of whether the transmission of the data block of lower priority is not successful. The reordering buffer cannot tell whether a missing data block has been preempted by a higher priority data block or whether the data block is still in H-ARQ transmission. For example, the Priority
2
reordering buffer R
2
does not know whether its third data block B
2
3
was preempted by one of the Priority
1
data blocks B
1
1
-B
1
4
or whether its data block B
2
3
is still in transmission. Where its third data block B
2
3
was preempted and no data block was received with the same H-ARQ processor as that of the data block B
2
3
within t
InterDigital Technology Corporation
Jung Min
Lee Andy
Volpe and Koenig P.C.
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