System and method for avoiding bus contention on a multiplexed b

Details System and method for avoiding bus contention on a multiplexed b System and method for avoiding bus contention on a multiplexed b

1995-08-24

1999-02-16

Donaghue, Larry D.

39580029, 3958003, 39580042, G06F 1300

Patent

active

058729925

ABSTRACT:
A bus interface unit within a processor ensures a delay period after the occurrence of a read operation to avoid bus contention on a multiplexed bus, When there is a requirement for a back-to-back read or write operation subsequent to the read bus cycle on a multiplexed bus it is important to allow devices, such as memory, sufficient time to reset after transmission of data. To avoid the bus contention problem that occurs after a read bus cycle, i.e, prevent a next address on the bus until the bus is in a tri-state condition, one embodiment inserts idle clock cycles subsequent to a read but not subsequent to a write, The present invention avoids bus contention on a multiplexed bus while providing flexibility in interfacing with a variety of memory devices, and providing a flexible processor design.

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Motorola MC68332 User's Manual, 4.3 "Chip-Select Submodule", published 1990, pp. 4-27 thru 4-46.

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