Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2004-08-04
2009-06-30
Hjerpe, Richard (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000
Reexamination Certificate
active
07554519
ABSTRACT:
The present invention provides a system and method for adjusting clock phase in a digital display. The display10may include a target analog-to-digital converter104that generates a first digital signal based on an analog input signal and a first clock signal (CLK1). The system100includes a first clock phase adjustment circuit108, which provides CLK1to the target analog-to-digital converter104. A second analog-to-digital converter106receives at least a portion of the analog input signal and a second adjusted clock signal (CLK2), and generates a second digital signal based on these inputs. A second clock phase adjustment circuit100is communicatively coupled to the second analog-to-digital converter106, and transmits CLK2to the second analog-to-digital converter. A controller112receives the second digital signal from the second analog-to-digital converter106and uses the signal to determine a preferred phase of CLK2. The controller112then causes the first clock phase adjustment circuit to adjust the phase of CLK1based on the preferred phase.
REFERENCES:
patent: 6285344 (2001-09-01), Everard et al.
patent: 2000338924 (2000-12-01), None
First Office Action issued Aug. 17, 2007 by the Patent Office of the People's Republic of China re corresponding Chinese Patent Application No. 200510098070.6, including English-language translation thereof.
Jiang Jiande
Lin Walter C.
DLA Piper (LLP) US
Hjerpe Richard
Kumar Srilakshmi K
Trident Microsystems (Far East) Ltd.
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