System and method for atomic access to an input/output device wi

Details System and method for atomic access to an input/output device wi System and method for atomic access to an input/output device wi

1989-11-17

1993-06-08

Fleming, Michael R.

Boots, shoes, and leggings

3642397, 3642435, 364DIG1, 3649266, 3649393, 364DIG2, G06F 1300

Patent

active

052186784

ABSTRACT:
A system (30) for atomic access to an I/O device with DMA includes a CPU (32) connected to a floating point processor (FPU) (34) by bus (36). The CPU (32) is connected by a system bus (38) to a random access memory (RAM) (40), a cache (42) and an interface (44) in graphics subsystem (45). The interface (44) is connected by bus (46) to graphics processor (48). In this system, graphics subsystem (45) is an I/O device, and atomic access to it is required. Command packet interface (44) to the graphics subsystem (45) transfers geometry and graphics context information from main memory (40) to the graphics subsystem (45). For such transfers, an application writes a list of commands to a physically contiguous locked-down memory buffer (47) in its own address space. Since the system (30) has DMA, the buffer (47) resides in the main memory system (40). When the buffer (47) is full, the CPU (32) tells the graphics subsystem (45), via a read from an I/O address on the graphics subsystem (45), that it should begin a transfer of the command packet. Status of the operation is returned as a result of the I/O read transaction. After initiating the command packet transfer, the graphics subsystem (45) parses the packet and executes the appropriate operations atomically.

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