Boots – shoes – and leggings
Patent
1992-12-31
1997-02-18
Donaghue, Larry D.
Boots, shoes, and leggings
395384, 364DIG1, 3642624, 36423223, 3642289, 3642517, G06F 938
Patent
active
056049129
ABSTRACT:
Tag monitoring system for assigning tags to instructions. A memory unit stores instructions to be executed by an execution unit. Before execution an instruction fetch unit decodes the instructions. A register file stores the decoded instructions. A queue having a plurality of slots containing tags which are used for tagging the decoded instructions. A control unit assigns the tags to decoded instructions, monitors the completion of executed instructions, and advances the tags in the queue upon completion of an executed instruction. The register stores a given decoded instruction at an address location in the register file defined by the tag assigned to that instruction. The register file also contains a plurality of read address enable ports and corresponding read output ports. Each of the slots from the queue is coupled to a corresponding one of the read address enable ports. Thus, a a decoded instruction is read out of a read output port enabled by the tag assigned to that decoded instruction in program order.
REFERENCES:
patent: 4881167 (1989-11-01), Sasaki et al.
patent: 4903196 (1990-02-01), Pomerene et al.
patent: 4992938 (1991-02-01), Cocke et al.
patent: 5067069 (1991-11-01), Fite et al.
patent: 5109495 (1992-04-01), Fite et al.
patent: 5125083 (1992-06-01), Fite et al.
patent: 5142633 (1992-08-01), Murray et al.
patent: 5214763 (1993-05-01), Blamer et al.
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5251306 (1993-10-01), Tran
patent: 5255384 (1993-10-01), Sachs et al.
patent: 5261071 (1993-11-01), Lyon
patent: 5285527 (1994-02-01), Crick et al.
patent: 5317720 (1994-03-01), Stamm et al.
patent: 5345569 (1994-09-01), Tran
patent: 5398330 (1995-03-01), Johnson
patent: 5487156 (1996-01-01), Popescu et al.
John L. Hennessy and David A. Patterson, Computer Architecture A Quantitative Approach, Ch. 6.4, 6.7, and p. 449, 1990.
Bruce D. Lightner and Gene Hill, "The Metaflow Lightning Chipset*", pp. 13-16, IEEE Publication, 1991.
Peleg et al., "Future Trends in Microprocessors: Out-of-Order Executions, Spec. Branching and Theis CISC Performance Potential", Mar. 1991.
Dwyer, A Multiple, Out-of-Order Instruction Issuing System for Superscalar Processors, (All), Aug. 1991.
Keller, R., "Look-Ahead Processors", Computing Surveys, vol. 7, No. 4, Dec. 1975.
Critical Issues Regarding HPS, A High Performance Microarchitecture, Yale N. Patt, Stephen W. Melvin, Wen-mei Hwu, and Michael C. Shebanow; The 18th Annual Workshop on Microprogramming, Pacific Grove, California, Dec. 3-6, 1985; IEEE Computer Order No. 653, pp. 109-116.
HPS, A New Microarchitecture: Rationale and Introduction, Yale N. Patt, Wen-mei Hwu, and Michael Shebanow; The 18th Annual Workshop on Microprogramming, Pacific Grove, California, Dec. 3-6, 1985; IEEE Computer Society Order No. 653, pp. 103-108.
Popescu et al., The Metaflow Architecture, IEEE Micro, vol. 11, No. 3, Jun. 1991, pp. 10-13 and 63-73.
Johnson, Superscalar Microprocessor Design, (Prentice-Hall), Inc., Englewood Cliffs, New Jersey, 1991).
Deosaran Trevor A.
Garg Sanjiv
Iadonato Kevin R.
Donaghue Larry D.
Seiko Epson Corporation
LandOfFree
System and method for assigning tags to instructions to control does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for assigning tags to instructions to control , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for assigning tags to instructions to control will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1609143