Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
Patent
1999-02-19
2000-07-18
Donaghue, Larry D.
Electrical computers and digital processing systems: processing
Processing architecture
Superscalar
712215, 712217, 712218, G06F 1500, G06F 930
Patent
active
060921765
ABSTRACT:
A tag monitoring system for assigning tags to instructions. A source supplies instructions to be executed by a functional unit. A register file stores information required for the execution of each instruction. A queue having a plurality of slots containing tags which are used for tagging the instructions. The tags are arranged in the queue in an order specified by the program order of their corresponding instructions. A control unit monitors the completion of executed instructions and advances the tags in the queue upon completion of an executed instruction. The register file stores an instruction's information at a location in the register file defined by the tag assigned to that instruction. The register file also contains a plurality of read address enable ports and corresponding read output ports. Each of the slots from the queue is coupled to a corresponding one of the read address enable ports. Thus, the information for each instruction can be read out of the register file in program order.
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Deosaran Trevor A.
Garg Sanjiv
Iadonato Kevin R.
Donaghue Larry D.
Seiko Epson Corporation
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