System and Method for assigning addresses to I/O devices in a co

Details System and Method for assigning addresses to I/O devices in a co System and Method for assigning addresses to I/O devices in a co

1994-02-28

1996-08-27

Shin, Christopher B.

3952002, 395828, 39549701, G06F 1300

Patent

active

055510531

ABSTRACT:
A method and system is provided for assigning addresses to input/output (I/O) devices in a control network, and for verifying addresses assigned to the I/O devices. The system comprises a logic controller providing memory into which a connectivity map may be programmed. The connectivity map defines a specific expected address for each I/O device in the system. The logic controller further provides an external controller bus and logic for downloading the connectivity map to an I/O bus manager connected to the logic controller via the external controller bus. The I/O bus manager provides logic for assigning the specific addresses to the I/O devices. Network nodes connect the I/O bus manager to I/O cluster units in the system, each network node including a multiplexer for multiplexing output signals from the I/O bus manager and a demultiplexer for demultiplexing input signals from the I/O cluster units, the multiplexing/demultiplexing functions provided by a controller area network (CAN) integrated circuit. Each I/O cluster unit includes a multiplexer for multiplexing input signals from the I/O devices and a demultiplexer for demultiplexing output signals from its associated network node, the multiplexing/ demultiplexing functions again provided by a controller area network (CAN) integrated circuit. Each I/O cluster unit provides means for manually requesting address assignments and a visual indication of addresses so assigned. Each I/O cluster unit also provides means to manually reject the address assigned to it by the I/O bus manager if the assigned address is not the expected address for the I/O cluster processor defined in the connectivity map.

REFERENCES:
patent: 4354258 (1982-10-01), Sato
patent: 4360870 (1982-11-01), McVey
patent: 4373181 (1983-02-01), Chisholm et al.
patent: 4660141 (1987-04-01), Ceccon et al.
patent: 4701878 (1987-10-01), Giinkel et al.
patent: 4725835 (1988-02-01), Schreiner et al.
patent: 4755934 (1988-07-01), Inoue
patent: 4769782 (1988-09-01), Iwanga
patent: 4803623 (1989-02-01), Klashka et al.
patent: 4964038 (1990-10-01), Louis et al.
patent: 5175822 (1992-12-01), Dixon et al.
patent: 5265241 (1993-11-01), Arnold et al.
patent: 5274771 (1993-12-01), Hamilton et al.
patent: 5276400 (1994-06-01), Jolissaint et al.
patent: 5394503 (1995-02-01), Dietz, Jr. et al.
patent: 5422631 (1995-06-01), Gertz
patent: 5428748 (1995-06-01), Davidson et al.
patent: 5444642 (1995-08-01), Montgomery et al.
patent: 5457791 (1995-10-01), Matsumoto et al.
Article entitled "Intel Chips Meet CAN Auto Specs", Electronic Buyer's News, Aug. 17, 1992.
Article entitled "Chips Push CAN Bus into Embedded World", Electronic Engineering Times, Aug. 24, 1992.
Motorola Semiconductor Technical Data brochure, .COPYRGT. 1991, entitled "Product Review MC68HC705X4 8-bit Microprocessor with on-board CAN Module".
Article entitled "Controller Chip Boosts CAN Protocol Usage", Electrical Wholesaling, Jul. 1992.

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