System and method for arbitrating accelerator requests

Details System and method for arbitrating accelerator requests System and method for arbitrating accelerator requests

1995-06-06

1998-10-06

Pan, Daniel H.

39518321, 395595, G06F 930, G06F 9345

Patent

active

058190260

ABSTRACT:
The present invention is a method and system for reducing delays due to a stream of digital data processing requests to a function specific hardware circuit. The system includes a first hardware stage implemented to perform the given function and a second parallel software code stage implemented to perform the same function. The hardware stage employs circuitry to implement the function whereas the software stage performs the function using software code including function specific processor instructions. The system also includes an arbitration stage that routes the data values to either of the hardware or software stages depending on the availability of the hardware stage and in accordance to pre-defined arbitration rules.

REFERENCES:
patent: 5394534 (1995-02-01), Kulakowski et al.
patent: 5475388 (1995-12-01), Gormish et al.
patent: 5561688 (1996-10-01), Jones, Jr.
patent: 5572340 (1996-11-01), Eckhardt et al.

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