Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2001-09-14
2004-07-27
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S119000, C702S121000, C702S122000
Reexamination Certificate
active
06768961
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a system and method for analyzing error information from a semiconductor fabrication process, and more particularly, to a system and method which accurately identifies systematic, repeated and random errors from wafer map data acquired during a semiconductor fabrication process.
BACKGROUND OF THE INVENTION
Semiconductors are made in production facilities, commonly referred to as “fabs.” A large fab may contain hundreds of automated tools that cooperatively work to convert circular silicon “wafers” (each consisting of dozens, hundreds, and even potentially thousands of chips) into functioning products. A “recipe” determines which operations these various tools perform, and is based upon the end-product that is to be manufactured. Recipes can be quite complicated, involving the use of hundreds of tools, each conducting specialized operations on the wafer, in a specific order, over a period of weeks or even months.
One of the challenges in these fabs is to control the manufacturing equipment and tools in a manner that minimizes variations and defects in the products being produced. For example, the manufacturing equipment and tools used within these fabs have a multitude of parameters which must be examined and controlled in order to minimize variations and errors.
One of the manufacturing tools typically used to manufacture chips is a “stepper.” A stepper images portions of the design onto the wafer multiple times, but does so in a step-wise fashion over groups of chips. The grouping of chips used is determined by the “reticle.” For example, a reticle layout may specify two rows of two columns of chips (a “two-by-two reticle layout”).
An excellent recipe does not guarantee a flawless batch of semiconductors. Random as well as systematic factors affect semiconductor quality. For example, a tool that is instructed to etch a batch of wafers for 1.8 seconds may instead etch for 1.81 seconds due to a slight inaccuracy in the timing mechanism of the tool. Such processing errors may cause several types of problems within chips. As a result, some chips may not function according to various benchmarks such as speed, and these substandard chips are much less valuable than the chips meeting the benchmarks. In addition, many of the substandard chips will not function at all. The percentage of properly functioning chips on a particular wafer is commonly referred to as the “yield” of the wafer.
The overall yield of a wafer may be divided into three unique yield categories. In the first category, systematic yield, the substandard or failing chips result from systematic factors or errors in the fab. Systematic errors can be desirably controlled, reduced and/or substantially eliminated once known. An example of a systematic error would be a tool that is not functioning properly. In the second category, random yield, the substandard or failing chips are caused by random factors or errors in the fab. An example of a random error would be dust that settled on the wafer as it was being fabricated. In the third category, repeated or “reticle” yield, the substandard or failing chips result from repeated factors or errors in the fab (e.g., the chips fail in a pattern consistent with the reticle layout). For example, in a two-by-two reticle layout, if the upper-left chip in each set of such four chips failed, a clear pattern related to the reticle or a reticle error would emerge. It is useful to an engineer in a fab who is tasked with managing chip yields to know which of these three yield factors to attribute certain failures to, because the corrective actions undertaken are highly dependent on the nature of the failures.
Improving yield is a major objective of the semiconductor industry and has a direct economic impact to the semiconductor industry. In particular, a higher yield translates into more devices that may be sold by the manufacturer. In order to improve yield, semiconductor manufacturing companies have implemented systems for collecting and analyzing error data. These prior systems often employ images and image processing algorithms and devices to document and/or identify errors within a wafer and to take action to prevent such errors from occurring in subsequent fabrications.
One device used by these prior systems is a “wafer map.” A wafer map provides a display of the chips on a wafer with each chip marked to indicate a result from the production process. For example, chips that pass a certain benchmark may be colored blue, whereas the ones that fail may be colored red. The pass/fail information conveyed by such a wafer map is a way of recording the yield of the wafer.
While such conventional systems and devices are effective to document the presence of errors in wafers, they suffer from some drawbacks. By way of example, these conventional systems provide no means to distinguish and/or identify the specific types of yield factors or errors present in a wafer or group of wafers. That is, these conventional systems only identify the presence of errors, and do not provide information as to whether the errors may be classified as systematic, random or repeated. As a result, output data provided by these conventional systems does not provide a fabrication engineer or professional with the information necessary to take the most effective corrective measures to prevent such problems in future fabrications or processes.
It is therefore desirable to provide a system and method which overcomes the drawbacks and limitations of conventional systems and methods, and which extracts accurate information regarding systematic, random and repeated errors from wafer map data acquired in a semiconductor fabrication process.
SUMMARY OF THE INVENTION
The present invention provides many advantages over conventional error information analysis methods and systems. By way of example and without limitation, the present invention accurately classifies chip errors on a wafer map in a plurality of categories, such as systematic, random and repeated failures. In this manner, the present invention allows a fabrication engineer or professional to provide corrective action which is purposely designed to overcome the specific type of errors or failures encountered.
According to a first aspect of the present invention, a system is provided for analyzing error information describing a plurality of failing chips on a semiconductor wafer. The system includes a controller which is adapted to receive the error information and to classify each of the plurality of failing chips in a unique one of a plurality of error categories.
According to a second aspect of the present invention, a system is provided for analyzing error information describing a plurality of failing chips on a semiconductor wafer. The system includes an input assembly which is adapted to accept and communicate the error information in the form of a wafer map; and a controller which is communicatively coupled to the input assembly and which receives the wafer map from the input assembly. The controller is adapted to classify each of the failing chips in a unique one of the group of categories including systematic failures, repeated failures and random failures, based upon the wafer map.
According to a third aspect of the present invention, a method for analyzing error information from a semiconductor manufacturing process is provided. The method includes the steps of: receiving wafer map data identifying a plurality of failing chips on a semiconductor wafer; and classifying each of the failing chips in a unique one of the group of categories including systematic errors, repeated errors, and random errors.
These and other features and advantages of the invention will become apparent by reference to the following specification and by reference to the following drawings.
REFERENCES:
patent: 6037614 (2000-03-01), He et al.
patent: 6252668 (2001-06-01), Hill
patent: 6292582 (2001-09-01), Lin et al.
patent: 6351712 (2002-02-01), Stoughton et al.
patent: 6445199 (2002-09-01), Satya et al.
Buckheit Jonathan B.
Wang Weidong
Gray Cary Ware & Freidenrich LLP
Hoff Marc S.
Suarez Felix
Yield Dyamics, Inc.
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