System and method for an efficient comparison operation of...

Details System and method for an efficient comparison operation of... System and method for an efficient comparison operation of...

2006-12-05

2011-10-11

Bullock, Jr., Lewis (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S210000

Reexamination Certificate

active

08037120

ABSTRACT:
An improved technique that considerably reduces required logic and computational time for determining whether the difference between two multi-bit vectors is equal to a given number or lies between given two numbers in a digital logic circuit. In one example embodiment, this is accomplished by receiving a first N-bit vector A [N−1:0] and a second N-bit vector B[N−1:0] in the digital logic circuit, where N is a non-zero positive number. A third N-bit vector is then obtained by performing a bit-wise AND (A [N−1:0] & ˜B[N−1:0]) operation using A[N−1:0] and ˜B[N−1:0]. Further, a fourth N-bit vector is obtained by performing a bit-wise XOR (A[N−1:0]^˜B[N−1:0]) operation using A[N−1:0] and ˜B[N−1:0]. The difference between the first N-bit vector A[N−1:0] and the second N-bit vector B[N−1:0] is then declared as equal to a given number or to be within a given range of two numbers (+m and +n, m<n) based on bit patterns in the third N-bit vector and the fourth N-bit vector.

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International Search Report for PCT/US07/24852, mailed Dec. 23, 2009, 2 pages.
Written Opinion for PCT/US07/24852, mailed Dec. 23, 2009, 6 pages.

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