Patent
1996-08-29
1998-06-16
Heckler, Thomas M.
G06F 108
Patent
active
057685711
ABSTRACT:
A system for altering a clock frequency to a logic controlling device that controls logic which runs at a fixed frequency slower than a frequency of a computer system running the logic. The system speeds up the clock signal to a logic controller when the logic controller is arbitrating between different operational requests. When the logic controller acknowledges a specific operational request, the clock controller immediately slows the clock signal down in order to allow a command strobe length that the logic device executing a specific operation request requires.
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patent: 5086387 (1992-02-01), Arroyo et al.
patent: 5432468 (1995-07-01), Moriyama et al.
patent: 5479644 (1995-12-01), Hongo
patent: 5561792 (1996-10-01), Ganapathy
patent: 5586308 (1996-12-01), Hawkins et al.
Jirgal James J.
Walker Gary
Heckler Thomas M.
Moss Allen J.
Moy Jeffrey D.
VLSI Technology Inc.
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