System and method for adaptive sigma-delta modulation

Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder

Reexamination Certificate

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C341S144000, C341S155000

Reexamination Certificate

active

06661363

ABSTRACT:

TECHNICAL FIELD AND BACKGROUND ART
The invention generally relates to signal processing, and more particularly, to analog to digital conversion using sigma-delta modulation. Sigma-delta (&Sgr;-&Dgr;) modulation is a widely used and thoroughly investigated technique for converting an analog signal into a high-frequency digital sequence. See, for example, “Oversampling Delta-Sigma Data Converters,” eds. J. C. Candy and G. C. Temes, IEEE Press, 1992, (hereinafter Candy) and “Delta-Sigma Data Converters,” eds. S. R. Northworthy, R. Schreier, G. C. Temes, IEEE Press, 1997, both of which are hereby incorporated herein by reference.
In &Sgr;-&Dgr; modulation, a low-resolution quantizer is incorporated within a feedback loop configuration in which the sampling frequency is much higher than the Nyquist frequency of the input signal (i.e., much higher than twice the maximum input frequency). In addition, the noise energy introduced in the quantizer is shaped towards higher frequencies according to a so called “noise-transfer-function” NTF(z), and the signal passes the modulator more or less unchanged according to a so called “signal-transfer-function” STF(z).
FIG.
1
(
a
) depicts a simple first order &Sgr;-&Dgr; modulator for a discrete time system having a subtraction stage
101
, an accumulator
102
(including an integrator adder
103
and a delay line
104
), a one-bit quantizer
105
, and a 1-bit digital-to-analog converter (DAC)
106
. In normal operation, an input signal x(n) within the range [−a, +a] is converted to the binary output sequence y
0
(n) &egr;±1. Quantizer
105
produces a+1 for a positive input and a−1 for a negative input. The output from quantizer
105
is fed back through DAC
106
and subtracted from input signal x(n) by subtraction stage
101
. Thus, the output of subtraction stage
101
represents the difference between input signal x(n) and the quantized output signal y
0
(n). As can be seen from FIG.
1
(
a
), the output of accumulator
102
represents the sum of its previous input and its previous output. Thus, depending on whether the output of the accumulator
102
is positive or negative, the one-bit quantizer
105
outputs a+1 or a−1 as appropriate. Herein, and in the appended claims, analog (physical) and digital representations of signals are distinguished from each other by labeling digital one or multi-bit signals with the subscript “0”.
In FIG.
1
(
b
), a linear model of FIG.
1
(
a
) is shown, and similarly includes a subtraction stage
107
, and an accumulator
111
(including an integrator adder
112
and a delay line
113
). Quantizer
105
is replaced by an adder
108
and a noise source
109
. To convert signal y(n) to y
0
(n), a comparator
110
for detection of the sign of y(n) is included. The basic relationship between the z-transforms of system input x(n), quantizer noise &ggr;
a
(n), and the two-level output sequence y(n) is:
Y
(
z
)=
z
−1
X
(
z
)+(1
−z
−1
)&Ggr;
a
(
z
)  (1)
The signal transfer function and noise-transfer function can be identified as STF(z)=z
−1
and NTF(z)=(1−z
−1
), respectively.
Quality of digital representation can be described by the signal-to-noise ratio
SNR
=
101



log
10



S
N
,
where S is the signal power and N is the noise power within a given bandwidth B. Regarding equation (1), the noise power N depends on both the noise transfer function NTF(z) and the overall amount of noise &Ggr;
a
(z) added in the quantization stage. To improve the SNR, two approaches can be pursued:
(a) for a given overall noise power &Ggr;
a
(z), i.e., for given quantizer levels ±a, modify the NTF(z) to remove more noise power from the base band by improved noise shaping, and
(b) for a given NTF(z), try to reduce the overall noise power introduced to the system.
Approach (a) can be achieved, for example, by increasing the order of the sigma-delta modulator, as described by Candy. For higher order modulators, the noise transfer function becomes NTF(z)=(1−z
−1
)
k
, which means an enhanced noise-shaping effect. For examples of approach (b) see Zierhofer C. M., “Adaptive sigma-delta modulation with one-bit quantization,” IEEE trans. CAS II, vol. 47, No. 5, May 2000 (hereinafter Zierhofer), and U.S. patent application for Adaptive Sigma-delta Modulation with One-bit Quantization, Ser. No.: 09/496,756, filed Feb. 3, 2000 (hereinafter U.S. patent application Ser. No.: 09/496,756), both of which are incorporated herein by reference, where a sigma-delta modulator is employed within a feedback loop configuration. It is shown that the input signal of this modulator applies within a reduced range, and thus the two levels of the quantizer can be reduced. As a consequence, less noise power is introduced to the system, and the SNR is improved.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the invention, a method and system for an adaptive sigma-delta (&Sgr;-&Dgr;) modulator with one bit quantization that improves the signal-to-noise (SNR) of a &Sgr;-&Dgr; modulator is presented. A difference signal is produced representing the difference between an analog input signal x(n) and a first adaptive feedback signal z(n), the amplitude of the analog input x(n) within a first range [−a, +a]. The difference signal is accumulated to produce a first accumulated signal representing an accumulation of the difference signal. The first accumulated signal is then quantized, creating a first quantized digital signal y
0
(n). Based on the first quantized digital signal y
0
(n) a first digital output signal z
0
(n) is produced, such that the instantaneous magnitude of the first analog feedback signal z(n) is substantially kept within the first range [−a, +a] and greater than the analog input signal's x(n) instantaneous magnitude. A digital-to-analog conversion is performed on the first digital output signal z
0
(n) to produce the first adaptive feedback signal z(n).
In related embodiments of the invention, the first quantized digital signal y
0
(n) produced includes a two-level digital output sequence. The two-level digital output may include values of +1 and −1. Producing the first digital output signal z
0
(n) may include multiplying the first quantized digital signal y
0
(n) by a step size c
0
(n). The step size c
0
(n) may be based on a set Y of code words, where Y={y
0
(n), y
0
(n−1), y
0
(n−2) . . . y
0
(n−n
x
)}, n
x
being a predetermined integer. Determining the step size c
0
(n) may include increasing the step size c
0
(n) if a majority of the code words are equal, or decreasing the step size c
0
(n) if the code words alternate. The step size c
0
(n) may be non-linear. Multiplying the first quantized digital signal y
0
(n) by a step size c
0
(n) may include using a look-up-table RAM.
Other related embodiments of the invention may further comprise high pass filtering the analog input signal x(n). In one embodiment of the invention, high pass filtering may include subtracting from the analog input signal x(n) a feedback signal based on the digital output signal z
0
(n). In another embodiment of the invention, high pass filtering may include producing a second accumulated signal az
0
(n) representing the accumulation of the first digital output signal z
0
(n). The second accumulated signal az
0
(n) is multiplied by a factor &thgr; to produce a multiplied signal w
0
(n). The analog input signal x(n) is then produced by subtracting from an analog pre-input signal x
p
(n) the second analog feedback signal w(n). In yet another embodiment of the invention, high pass filtering the analog input signal x(n) may include producing a second accumulated signal az
0
(n) representing the accumulation of the first digital output signal z
0
(n). A digital signal w
0
(n) is produced using an embedded numeric multibit sigma-delta modulator, the digital signal w
0
(n) representing the accumu

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