System and method for adaptive run-time reconfiguration for...

Details System and method for adaptive run-time reconfiguration for... System and method for adaptive run-time reconfiguration for...

2007-01-23

2007-01-23

Tsai, Henry W. H. (Department: 2181)

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

C712S037000

Reexamination Certificate

active

10881146

ABSTRACT:
A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.

REFERENCES:
patent: 6298366 (2001-10-01), Gatherer et al.
patent: 2002/0188826 (2002-12-01), Rose et al.
patent: 2005/0027970 (2005-02-01), Arnold et al.

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