Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2001-06-28
2004-12-07
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
With measuring or testing
C438S428000
Reexamination Certificate
active
06828162
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to semiconductor processing, and in particular to a system for monitoring and controlling boron phosphorous doped silicon oxide (BPSG) deposition and reflow.
BACKGROUND
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there have been, and continue to be, efforts toward scaling down device dimensions (e.g., at sub-micron levels) on semiconductor wafers and to increase the number of layers of such devices on a chip. In order to accomplish such high device packing densities, smaller and smaller features sizes are required. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, and the surface geometry, such as corners and edges, of various features. The smaller features are separated by layers of thin dielectric films (e.g. BPSG). But the deposition of the thin dielectric film BPSG is not conformal, which negatively impacts the ability to achieve desired feature sizes and packing densities.
The process of manufacturing semiconductors, or integrated circuits (commonly called ICs, or chips), typically consists of more than a hundred steps, during which hundreds of copies of an integrated circuit may be formed on a single wafer. Generally, the process involves creating several patterned layers on and into the substrate that ultimately forms the complete integrated circuit. This layering process creates electrically active regions in and on the semiconductor wafer surface. Thin dielectric films, such as BPSG, are used in fabricating chips.
The requirement of small features with close spacing between adjacent features requires sophisticated manufacturing techniques, including high-resolution photolithographic processes, and controlling dielectric layer deposition. Fabricating a semiconductor using such sophisticated techniques may involve a series of steps including cleaning, thermal oxidation or deposition, masking, developing, etching, baking and doping.
Wafers may be pre-cleaned using, for example, high-purity, low-particle chemicals. The silicon wafers may be heated and exposed to ultra-pure oxygen in diffusion furnaces under carefully controlled conditions to form a silicon dioxide film of uniform thickness on the surface of the wafer. Once the wafer is clean, layers of oxide and photo resist can be applied. The masking step is used to protect one area of the wafer while working on another area. This process is referred to as photolithography or photo-masking. A photo resist, or light-sensitive film, is applied to the wafer, giving it characteristics similar to a piece of photographic paper. A photo aligner aligns the wafer to a mask, and then projects an intense light through the mask and through a series of reducing lenses, exposing the photo resist with the mask pattern. Precise alignment of the wafer to the mask prior to exposure is critical.
In the developing step, the wafer is then “developed”, wherein selected portions of the photo resist are hardened. The portions of the photo resist that were not hardened may be removed, exposing the oxide layer beneath. Once the oxide is exposed, the wafer may be etched, to remove undesired areas of oxide. The etching may be accomplished, for example, by a chemical solution or plasma (gas discharge). The photo resist remaining after the undesired oxide has been removed is then removed using additional chemicals or plasma to reveal the desired pattern in the oxide. The wafer is then inspected to ensure the image transfer from the mask to the top layer is correct.
In the doping step, atoms with one less electron than silicon (e.g. boron), or one more electron than silicon (e.g. phosphorous), are introduced into the area exposed by the etch process to alter the electrical character of the silicon. These areas are called P-type (boron) or N-type (phosphorous) to reflect their conducting characteristics. The thermal oxidation, masking, etching and doping steps may be repeated several times until the last “front end” layer is completed (e.g. all active devices have been formed).
ICs may consist of more than one layer, the layers being separated by dielectric layers. Irregularities in the dielectric layers may create problems, like electrical shorting between features and/or layers, for example. Further, dielectric layers that are too thick may prevent achieving desired packing densities and may reduce the number of layers that may be deposited on an IC. Further still, dielectric layers with irregular surfaces may require more material to be deposited to fabricate subsequent layers than would be required by a more uniform surface.
BPSG may be deposited, for example, by a plasma or vapor deposition process. Ideally, such a process would deposit a uniform layer of BPSG on a wafer, but variations occur both between fabrication runs and within wafers. Since there since there may be irregularities and since uniformity in BPSG layer deposition is desired, the non-conformal deposition of BPSG may require local planarization to achieve the desired surface plane.
Thus, an efficient system and/or method to monitor and control the BPSG deposition and reflow for local planarization process is desired to increase chip quality.
SUMMARY
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention provides a system that facilitates controlling boron phosphorous doped silicon oxide (BPSG) deposition and reflow for local planarization. An exemplary system may employ one or more light sources arranged to project light onto one or more portions of a wafer upon which BPSG is deposited and one or more light sensing devices (e.g. photo detector, photodiode) for detecting light reflected by, and/or allowed to pass through the BPSG. The light reflected from, and/or passing through the BPSG is indicative of at least one parameter of the BPSG deposition and reflow for local planarization process (e.g.uniformity of surface).
A plurality of reflow controlling components are arranged to correspond to a particular wafer portion. The reflow controlling components may be, for example, heat lamps, baking plates, and/or fluid conducting apparatus. It is to be appreciated by one skilled in the art that any suitable reflow controlling component may be employed with the present invention. Each reflow controlling component may be responsible for heating and/or cooling one or more particular wafer portions. The reflow controlling components are selectively driven by the system to regulate the reflow of BPSG for local planarization on a wafer portion. The BPSG deposition and reflow is monitored by the system by analyzing the light reflected from and/or passing through the wafer. As a result, more optimal BPSG deposition and reflow is achieved by controlling the temperatures applied to the portions of the wafer, which in turn increases chip quality.
An aspect of the present invention provides a system for monitoring and controlling boron phosphorous doped silicon oxide (BPSG) deposition and reflow comprising: at least one reflow controlling component operative to control the temperature of at least one portion of a wafer; a reflow controlling component driving system for driving the at least one reflow controlling component; a system for directing light to the at least one portion of the wafer; a measuring system for measuring BPSG deposition parameters based on light reflected from the at least one portion of the wafer; and a processor operatively coupled to the measuring system and the reflow controlling component driving system, the processor receiving BPSG deposition data from the
Halliyal Arvind
Singh Bhanwar
Subramanian Ramkumar
Templeton Michael K.
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Coleman W. David
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