Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2001-04-02
2002-11-26
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S108000
Reexamination Certificate
active
06486715
ABSTRACT:
FIELD
The present invention relates generally to driving circuits for capacitive load, and more particularly to a system and method for achieving fast switching of analog voltages on a large capacitive load.
BACKGROUND
A conventional driving circuit or driver for driving a capacitive load typically consists of a signal input, a signal output and an amplifier or an analog voltage buffer to drive the load between two or more voltages. Two important properties of a buffer are power consumption and response time, which is the time required for the buffer to reach a specified output following the application of a specified input under specified operating conditions. Generally, these two properties cannot be optimized simultaneously. This is because improving response time means increasing unity gain frequency and slew rate, the ability of an amplifier to reflect a change in the input in the output quickly, both of which require increasing bias current of the buffer. Thus, reducing response time requires increasing power consumption, and reducing power consumption results in a increase in response time.
There are prior art designs for buffers that dynamically increase the bias current to improve the slew rate only when needed, thereby improving the response time while limiting the increase in power consumption. However, the design of such a buffer is complicated and exhibits several undesirable characteristics such as instability. These dynamic buffers also produce significant noise on supply lines during voltage transitions when the needed charge is drawn quickly, thereby requiring the addition of complex and often costly filters.
The above shortcomings of conventional driver circuits are particularly a problem for driving circuits used, for example, to drive floating gates of FETs (Field Effect Transistors) used in semiconductor devices such as storage elements or cells in non-volatile memory systems, such as electrically erasable programable read-only memory (EEPROM) or flash memory. The floating gate in an FET is not directly connected to the rest of the device and thus appears to the driving circuit as a purely capacitive load. This capacitive load can be quite large since a large number of storage elements in the non-volatile memory system, typically from 16 thousand to 10 million storage elements depending on the size of the memory, must be switched simultaneously between a programming voltage and a verify voltage. A programming voltage is a voltage applied to store information in the storage element as a charge on the floating gate. A verify voltage is used to determine if the storage element has stored a proper amount of charge and therefore the information. The transition between programming voltage and verify voltage and vice versa must be fast to achieve satisfactory write-performance. However, such driver circuits are frequently used in portable, battery operated devices in which the available power is limited and therefore must be conserved. Morever, the power for the driver circuit is usually supplied by an on-chip high-voltage-pump. Because both the generation and consumption of power produce heat that must be dissipated for the devices on the chip to function properly, conserving power is again necessary. Thus, increasing the bias current to improve the response time in the buffer is generally not desirable.
SUMMARY
Accordingly, there is a need for a driving circuit for driving a capacitive load that provides an improved response time to drive the load between two or more voltages without increasing power consumption of a buffer in the driving circuit.
In one aspect, the present invention provides a driver for driving a capacitive load, the driver having a load buffer with an input for receiving an input voltage (V
IN
), and an output for coupling an output voltage (V
OUT
) to the capacitive load. The load buffer is configured to drive V
OUT
between a first voltage level (V
1
) and a second, higher voltage level (V
2
) in response to a change in V
IN
. The driver further includes a reserve circuit configured to reduce the time for V
OUT
to transition between V
1
, and V
2
. The reserve circuit has a reserve capacitor or capacitor, a reserve buffer, a switch for coupling the reserve capacitor to the capacitive load and a controller for opening and closing the switch. The reserve buffer has an input for receiving an input voltage (V
RES
—
IN
), and an output for coupling an output voltage (V
RES
—
OUT
) to the reserve capacitor to charge the capacitor. The controller is configured to operate the switch to couple the reserve capacitor to the capacitive load when V
OUT
is being driven between V
1
and V
2
. Generally, the controller is coupled to the input of the load buffer, and is configured to operate the switch when a change in V
IN
is required.
In one embodiment, the reserve buffer includes a negative feedback loop to provide a gain that is substantially equal to unity. The reserve buffer is configured so that when V
IN
equals V
1
, V
RES
—
IN
has a steady state value of V
2
+a, and when V
IN
equals V
2
, V
RES
—
IN
has a steady state value of V
1
−a, where a equals (V
2
−V
1
)C
LOAD
/C
RES
, and where C
LOAD
is the capacitance of the capacitive load and C
RES
is the capacitance of the reserve capacitor.
In another embodiment, the driver includes a second switch for electrically isolating the capacitive load from the output of the load buffer. The second switch is operated by the controller to open when V
OUT
is being driven between V
1
and V
2
. Desirably, the second switch is operated by the controller to simultaneously open when the first switch is closed and to close when the first switch is opened.
In yet another embodiment, the reserve circuit includes first and second reserves capacitors, C
RES
—
A
and C
RES
—
B
, and first and second reserve buffers having inputs adapted to receive first and second input voltages, V
RES
—
IN
—
A
and V
RES
—
IN
—
B
respectively, and outputs adapted to couple first and second output voltage, V
RES
—
OUT
—
A
and V
RES
—
OUT
—
B
respectively, to charge C
RES
—
A
and C
RES
—
B
. A single pole, double throw switch capable of alternately coupling C
RES
—
A
and C
RES
—
B
to the capacitive load, is operated by a controller to alternately couple C
RES
—
A
and C
RES
—
B
to the capacitive load when V
OUT
is being driven between V
1
and V
2
.
The driver of the present invention is particularly useful in non-volatile memory systems such as a flash memory having a number of storage elements or cells with a number of Field Effect Transistors (FETs), each of the FETs having a gate coupled to the driver, and the driver configured to periodically drive the gates between a programming-voltage and a verify-voltage. Generally, the non-volatile memory system further includes a high-voltage-pump to supply voltage to both the load buffer and the reserve buffer. In one version of this embodiment, the storage elements, the driver and the high-voltage-pump are fabricated on a single semiconductor substrate.
In another aspect, a method is provided for operating the driver of the present invention. In the method, when V
IN
changes from V
1
to V
2
or from V
2
to V
1
, the load buffer is then operated to drive V
OUT
from V
1
to V
2
or from V
2
to V
1
in response to the change in V
IN
. At the same time, or shortly thereafter, the switch is closed to couple the reserve capacitor to the capacitive load, thereby reducing the time necessary for the capacitive load to transition between V
1
and V
2
. Generally, the step of closing the switch involves closing the switch only briefly until V
OUT
has reached V
1
or V
2
.
In one embodiment, as described above, the reserve circuit further includes a reserve buffer coupled to the reserve capacitor, and the method further includes the steps of charging the reserve capacitor to a voltage level (V
RES
—
OUT
) using the reserve buffer, and discharging the reserve capacitor into the capacitive load to raise the voltage applied to the capacitive load from V
1
to V
2
.
Gongwer Geoffrey S.
Khalid Shahzad
Le Dinh T.
SanDisk Corporation
Skjerven Morrill LLP
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