System and method for accelerating arithmetic decoding of...

Details System and method for accelerating arithmetic decoding of... System and method for accelerating arithmetic decoding of...

2004-06-18

2008-12-30

Malzahn, David H (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07472151

ABSTRACT:
Presented herein is a system and apparatus for accelerating arithmetic decoding of encoded data. In one embodiment, there is presented a symbol interpreter for decoding CABAC coded data. The symbol interpreter comprises a first memory, a CABAC decoding loop, and a syntax assembler. The first memory receives a bitstream comprising the CABAC coded data at a channel rate. The CABAC decoding loop decodes the CABAC symbols at the channel rate, and comprises an arithmetic decoder for generating binary symbols from the CABAC coded data at the channel rate. The syntax assembler decodes the binary symbols at a consumption rate.

REFERENCES:
patent: 6646578 (2003-11-01), Au
patent: 2003/0215018 (2003-11-01), MacInnis
patent: 2004/0240559 (2004-12-01), Prakasam et al.
patent: 2005/0259747 (2005-11-01), Schumann
patent: 2005/0262375 (2005-11-01), Schumann

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