System and method for a whole-chip electrostatic discharge...

Details System and method for a whole-chip electrostatic discharge... System and method for a whole-chip electrostatic discharge...

2008-07-01

2008-07-01

Sherry, Michael J (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

C361S056000, C361S091300

Reexamination Certificate

active

07394638

ABSTRACT:
The embodiments of the present invention introduced and taught herein are directed to a whole-chip ESD protection arrangement that is independent of relative supply rail voltage and supply sequencing, thereby enabling ESD conduction path during ESD event and isolating the ESD conduction path during the power up and power down modes of the chip. An embodiment of the present invention uses the bi-directional R-C clamp with transistorized arrangements between powered rails and avoids the drawback of using uni-directional Clamps or diode array for clamping that consumes large silicon area, requires power sequencing and is prone to noise coupling between power rails.

REFERENCES:
patent: 5532626 (1996-07-01), Khayat
patent: 5886862 (1999-03-01), Anderson et al.
patent: 2004/0125521 (2004-07-01), Salling et al.
Ming-Dou Ker, Whole-Chip ESD Protection Design with Efficient VDD-to-VSS ESD Clamp Circuits for Submicron CMOS VLSI, Jan. 1999, IEEE, vol. 46, No. 1, pp. 173-183.

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