System and method for a fast fourier transform architecture...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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C708S409000

Reexamination Certificate

active

07496618

ABSTRACT:
A Fourier transform architecture and system for FFT and IFFT processing within multicarrier transceiver is disclosed that includes a programmable butterfly component, a memory and a programmable address generation unit. The architecture includes a butterfly component configured to perform a plurality of radix butterfly calculations, and a four bank memory configured to operate on sample data. The architecture further includes a programmable address generation unit coupled to the pipeline to enable the architecture to perform calculations independent of Fourier-based algorithms. A method for addressing memory banks for an FFT pipeline includes expressing an index in radix notation, computing a bank address for a bank memory, converting the bank address to a reduced size by ignoring one or more bits, and calculating the bank address within the reduced memory bank.

REFERENCES:
patent: 6366936 (2002-04-01), Lee et al.
patent: 2004/0143616 (2004-07-01), Kang
patent: 2005/0102341 (2005-05-01), Taunton
patent: 2006/0075010 (2006-04-01), Wadleigh et al.

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