Electrical connectors – Preformed panel circuit arrangement – e.g. – pcb – icm – dip,... – With provision to conduct electricity from panel circuit to...
Patent
1998-08-24
1999-06-29
Abrams, Neil
Electrical connectors
Preformed panel circuit arrangement, e.g., pcb, icm, dip,...
With provision to conduct electricity from panel circuit to...
H01R 909
Patent
active
059159774
ABSTRACT:
An interconnect and system for establishing temporary electrical communication with semiconductor components having contact bumps are provided. The interconnect includes a substrate with patterns of contact members adapted to electrically contact the contact bumps. The substrate can be formed of a material such as ceramic, silicon, FR-4, or photo-chemically machineable glass. The contact members can be formed as recesses covered with conductive layers in electrical communication with conductors and terminal contacts on the substrate. Alternately, the contact members can be formed as projections adapted to penetrate the contact bumps, as microbumps with a rough textured surface, or as a deposited layer formed with recesses. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare bumped dice or bumped chip scale packages.
REFERENCES:
patent: 4937653 (1990-06-01), Blonder
patent: 4969828 (1990-11-01), Bright et al.
patent: 5006792 (1991-04-01), Malhi et al.
patent: 5072289 (1991-12-01), Sugimoto et al.
patent: 5088190 (1992-02-01), Malhi et al.
patent: 5172050 (1992-12-01), Swapp
patent: 5206585 (1993-04-01), Chang et al.
patent: 5289631 (1994-03-01), Koopman et al.
patent: 5326428 (1994-07-01), Farnworth et al.
patent: 5329423 (1994-07-01), Scholz
patent: 5408190 (1995-04-01), Wood et al.
patent: 5414372 (1995-05-01), Levy
patent: 5420520 (1995-05-01), Anschel et al.
patent: 5440240 (1995-08-01), Wood et al.
patent: 5451165 (1995-09-01), Cearley-Cabbiness
patent: 5453701 (1995-09-01), Jensen et al.
patent: 5477160 (1995-12-01), Love
patent: 5481205 (1996-01-01), Frye et al.
patent: 5483741 (1996-01-01), Akram et al.
patent: 5487999 (1996-01-01), Farnworth
patent: 5495179 (1996-02-01), Wood et al.
patent: 5500605 (1996-03-01), Chang
patent: 5517125 (1996-05-01), Posedel et al.
patent: 5519332 (1996-05-01), Wood et al.
patent: 5523696 (1996-06-01), Charlton et al.
patent: 5530376 (1996-06-01), Lim et al.
patent: 5534785 (1996-07-01), Yoshizaki et al.
patent: 5541525 (1996-07-01), Wood et al.
patent: 5543725 (1996-08-01), Lim et al.
patent: 5581195 (1996-12-01), Lee et al.
patent: 5592736 (1997-01-01), Akram et al.
patent: 5607818 (1997-03-01), Akram et al.
patent: 5625298 (1997-04-01), Hirano et al.
patent: 5691041 (1997-11-01), Frankeny et al.
patent: 5716218 (1998-02-01), Farnworth et al.
patent: 5783461 (1998-07-01), Hembree
patent: 5789271 (1998-08-01), Akram
patent: 5808360 (1998-09-01), Akram
patent: 5815000 (1998-09-01), Farnworth et al.
patent: 5834366 (1998-11-01), Akram
patent: 5869974 (1999-02-01), Akram et al.
Mul, Gary K. et al., Design Optimization for C4 Bare Die Burn-in and Test Carrier/Socket Assembly (with Statistical Considerations), The International Journal of Microcircuits and Electronic Packaging, vol. 19, No. 2, 2nd Qtr 1996, pp. 128-137.
Miyake, K., et al, "Connectivity Analysis of New "Known Good Die" Connection System Using Microbumps", Proceedings of IMC, pp. 156-161, 1994.
EIAJ/Area Array Subcommittee/Memory CSP WG, JWG#2-8, San Diego, advertising brochure, Jun., 1995.
"Science Over Art. Our New IC Membrane Test Probe", Packard Hughes Interconnect, advertising brochure, 1993.
"Cobra.TM. technology, makes Wentworth Labs the world's most advanced probe card manufacturer,", Wentworth Laboratories, 1996.
Foo, See-Hack and Prokopchak, Lina., "Known Good Die: A Commerical Solution for Burn-In and Test Before Packaging", Aehr Test Systems, presented at Semicon Japan, Dec. 1994.
Akram Salman
Farnworth Warren M.
Hembree David R.
Jacobson John O.
Wark James M.
Abrams Neil
Gratton Stephen A.
Micro)n Technology, Inc.
Patel T C
LandOfFree
System and interconnect for making temporary electrical connecti does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and interconnect for making temporary electrical connecti, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and interconnect for making temporary electrical connecti will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1370314