System and device to interface asynchronous apparatuses

Details System and device to interface asynchronous apparatuses System and device to interface asynchronous apparatuses

1987-09-23

1990-02-06

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

369 60, H03K 5135

Patent

active

048993522

ABSTRACT:
A system for interfacing asynchronous machines. The system includes a single-port RAM (Random Access Memory) synchronized with the master clock of only one of the asynchronous machines, and a FIFO (first in/first out) memory. The devices to implement this system consist of a single-port RAM, an FIFO memory, two counters, one of which is a write counter and the other is a read counter, a multiplexer which selects one of the two counters, and a RAM access control logic which generates the RAM control signals and the counter enabling signals and the above mentioned multiplexer select signal.

REFERENCES:
patent: 4271483 (1981-06-01), Baldwin et al.
patent: 4348754 (1982-09-01), Haynes et al.
patent: 4429386 (1984-01-01), Graden
patent: 4661966 (1987-04-01), Schreiner

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