Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2007-12-19
2009-12-08
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S057000, C327S211000, C327S215000
Reexamination Certificate
active
07629817
ABSTRACT:
In particular embodiments, an apparatus includes a first transistor connected at the gate to a first input signal voltage and a second transistor connected at the gate to a second input signal voltage. The apparatus further includes a deactivation element coupled to the transistors, the deactivation element being operable to deactivate the first and second transistors by selectively transmitting a deactivation current to a first terminal of the first transistor and a second terminal of the second transistor thereby raising a voltage on the first and second terminals to a value large enough to deactivate the first and second transistors. In particular embodiments, activating the first or second transistor transmits a signal from the apparatus and deactivating the first and second transistors prevents the signal from being transmitted from the apparatus.
REFERENCES:
patent: 4004284 (1977-01-01), Heeren
patent: 5289055 (1994-02-01), Razavi
patent: 5396125 (1995-03-01), Wong
patent: 5986494 (1999-11-01), Kimura
patent: 6025736 (2000-02-01), Vora et al.
patent: 6472920 (2002-10-01), Cho et al.
patent: 6798249 (2004-09-01), Wong et al.
patent: 7084683 (2006-08-01), Nix
patent: 7375568 (2008-05-01), Amamiya
patent: 7382175 (2008-06-01), Maruyama et al.
M. Matsui, H. Hara, Y. Uetani, K. Lee-Sup, T. Nagamatsu, Y. Watanabe, A. Chiba, K. Matsuda, T. Sakurai, “A 200 MHz 13 mm22-D DCT macrocell using sense-amplifying pipeline flip-flop scheme”, IEEE Journal of Solid-State Circuits, vol. 29, n. 12, p. 1482-1490, Dec. 1994.
J. Cao et al., “OC-192 transmitter and receiver in standard 0.18- μm CMOS”, IEEE Journal of Solid-State Circuits, vol. 37, No. 12, p. 1768-1780, Dec. 2002.
J. Rogers, J. Long, “A 10-Gb/s CDR/DEMUX WithLCDelay Line VCO in 0.18-μm CMOS”, IEEE Journal of Solid-State Circuits, vol. 37, No. 12, p. 1781-1789, Dec. 2002.
J. Lee, B. Razavi, “A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology”, IEEE Journal of Solid-State Circuits, vol. 38, No. 12, p. 2181-2190, Dec. 2003.
A. Ong et al., “A 40-43 Gb/s clock and data recovery IC with integrated SFI-5 1:16 demultiplexer in SiGe technology”, IEEE Journal of Solid-State Circuits, vol. 38, No. 12, p. 2155-2168, Dec. 2003.
M. Megheli, et al., “A 0.18μm SiGe BiCMOS Receiver and Transmitter Chipset for SONET OC-768 Transmission Systems,” ISSCC p. 230, Feb. 2003.
A. Koyama, et al., “43Gb/s Full-Rate-Clock 16:1 Multiplexor and 1:16 Demultiplexor with SFI-5 Interface in SiGe BiCMOS Technology,” ISSCC, p. 232, Feb. 2003.
J. Yen, et al., “A Fully Integrated 43.2Gb/s Clock and Data Recovery and 1:4 DEMUX IC in InP HBT Technology,” ISSCC, p. 240, Feb. 2003.
Y. Okaniwa et al., “A 0.11 μm CMOS clocked comparator for high-speed serial communications”, Symp. on VLSI Circuits, p. 198-201, Jun. 2004.
J. Lee, “High-speed circuit designs for transmitters in broadband data links”, IEEE Journal of Solid-State Circuits, vol. 41, No. 5, p. 1004-1015, May 2006.
Nedovic Nikola
Walker William W.
Baker & Botts L.L.P.
Fujitsu Limited
Wells Kenneth B.
LandOfFree
System and apparatus for aperture time improvement does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and apparatus for aperture time improvement, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and apparatus for aperture time improvement will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4088153