Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Reexamination Certificate
2001-04-16
2004-07-06
Nguyen, Nam (Department: 1753)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
C205S123000, C205S125000, C205S205000, C428S901000, C439S055000
Reexamination Certificate
active
06758958
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to methods and systems for plating conductive patterns.
TECHNOLOGICAL BACKGROUND
In the solid state electronics industry, a plurality of components being active devices as well as passive devices are processed on a surface of a semiconductor wafer for instance to form an integrated circuit. To form these integrated circuits metallization structures are requested both as a part of the aforementioned devices and to interconnect these devices. The formation of such metallization structures includes the plating of a conductive pattern, being part of a metallization structure and being formed at a first surface of a substrate, such as a wafer. Particularly this first surface can be the front side or the back side of the wafer.
One of the issues involved is the plating of this first surface of a substrate without exposing a second surface of a wafer, opposite to the first surface, to a plating solution. Particularly, exposure, even partly, would result in unwanted wetting, plating and/or corroding of other surfaces. Furthermore to be able to deposit a material by electroplating, the plating solution must be in contact with the first surface of the substrate comprising the conductive patterns to be plated and two electrically connectable electrodes have to be provided. Usually, the first electrode is immersed in the plating solution, while the second electrode has to be electrically connected to the conductive patterns to be plated. State-of-the-art plating techniques usually contact peripheral regions of the first surface of a substrate, comprising the conductive patterns to be plated. These peripheral contact regions are electrically connected to the second electrode as well as to the conductive patterns to be plated.
A problem is that often long metal lines are required to connect each conductive pattern to be plated with the contact in the peripheral region. Particularly, this is a problem when one wants to perform plating on wafer scale because the differences in distance between conductive patterns to be plated being located near the edges of the wafer and in the center of the wafer are huge. These differences are typically in the centimeter range. Consequently also the differences in resistance of the metal lines connecting the respective conductive patterns can be huge. This often results in a highly non-uniform plating process. All these metal connections between the conductive patterns to be plated and the peripheral regions can not be easily removed after the plating process and moreover, a lot of wafer-area is required to provide these connections thereby inhibiting dense integration. Another problem is that the contact means in the peripheral regions are exposed to the plating solution. These contact means become parasitically plated and have to be cleaned regularly. A further problem can arise if the contact means do not simultaneously can be used as sealing means, then extra sealing means are required. These sealing means should then be positioned between the contact means and the edges of the wafer in order to avoid leakage of the plating solution to another surface of the wafer. Consequently, this leads again to a further decrease of the available area which can be plated.
AIM OF THE INVENTION
The invention presents methods and systems for plating conductive patterns which at least result in a high uniformity and avoid parasitical plating effects.
SUMMARY OF THE INVENTION
In an aspect of the invention a plating system is disclosed for plating on a plurality of conductive patterns formed at a surface of a substrate. A plating solution is applied on this surface and the exposure of other surfaces of the substrate to the plating solution is inhibited. A first electrode of the system is immersed in the plating solution while the second electrode is in contact with another surface of the substrate. The conductive patterns to be plated are temporarily electrically connected with the second electrode resulting in a uniform and selective deposition over the exposed surface of the substrate. Particularly, according to this aspect of the invention, a system is disclosed for plating on at least one conductive pattern, said conductive pattern being positioned at a first surface of a substrate having at least a first surface and a second surface, said system comprising:
a support with an electrically connectable electrode thereon;
a sealing element to inhibit the exposure of the second surface of the substrate to a plating solution; and
wherein said substrate is placeable on said support such that said electrode is in contact with said second surface of said substrate and wherein a contact to said first surface of said substrate is provided, said conductive pattern being temporarily electrically connected with said contact and said contact being electrically connected with said electrode.
In another aspect of the invention, a substrate is disclosed having at least a first surface and a second surface opposite to said first surface, said first surface being exposable to a plating solution, said substrate comprising
a conductive pattern being positioned at said first surface of a substrate;
a contact to the first surface of the substrate; and
said conductive pattern being temporarily electrically connected by a polysilicon or an amorphous silicon conductor with said contact and said contact being electrically connected with said second surface.
In a further aspect of the invention, a method is disclosed for plating on at least one conductive pattern formed at a surface of a substrate, said substrate having at least a first surface and a second surface, said method comprising the steps of:
placing the substrate on an electrode being part of a plating holder such that said second surface of said substrate is in contact with said electrode and said conductive pattern is temporarily electrically connected to said conductive pattern; and
applying a plating solution on said first surface of said substrate thereby inhibiting exposure of said second surface to said plating solution.
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Arquint Philippe
Baert Kris
Gumbrecht Walter
Steenkiste Filip Van
Interuniversitair Micro-Elektronica Centrum
Knobbe Martens Olson & Bear LLP
Mutschler Brian
Nguyen Nam
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