Synthesizable architecture for all-digital minimal jitter freque

Details Synthesizable architecture for all-digital minimal jitter freque Synthesizable architecture for all-digital minimal jitter freque

1996-07-22

1998-01-06

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synthesizer

327106, 327107, 327151, 327160, 327164, 364718, 364721, H04L 2720

Patent

active

057059454

ABSTRACT:
An architecture and system for the implementation of an all digital frequency synthesizing system is described. The frequency synthesizing system has a count series retention table that contains a series of count integers that are selected by a count signal that chooses which series of the integers are to be linked to a periodic input reference frequency counter. The periodic input reference frequency counter will count a number of periods of a periodic input reference frequency and when the counter has reached the number of counts that is equal to the number of the count integer, the periodic output frequency will be toggled from logic level to another logic level. A new periodic output frequency period can be chosen by selecting a new series of count integers in the count retention table. This architecture is structured such that it can be implemented in an automated logic design system.

REFERENCES:
patent: 4947382 (1990-08-01), Lesea
patent: 5430764 (1995-07-01), Chren, Jr.
patent: 5467294 (1995-11-01), Hu et al.
"Phase Locked Loops: Theory, Design and Application" by Best, McGraw-Hill Inc. 1993, pp. 202, 214, 216.

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